One can measure negative voltage with a dual slope ADC, if one has positive and negative references available. Alternatively one can use an offset to the input (e.g. zero at the integrator).
With a +7.5 V and -2.5 V supply would allow only 7.5 V as maximum at the input. The integration cap requirement is set by the maximum input, not the reference voltage. So it would be C=(integrationTime*Vin_max)/(Vsat*R). Vsat depends on where the integrator starts. Starting at 0 and thus allowing 7.5 V at the input there are only 2.5 left for Vsat, if there is no special provision for the reset circuit. So the integration cap would need to be even larger or the resistor larger. 20 ms integration time would also be an option.
For a larger Vsat, one could use a divider or diodes to limit the switch voltage.
To test linearity, at this level the method of choice would normally be a more linear DMM or calibrator / Kelvin-Varlay divider.
The main part to worry about is the large range INL, not so much the DNL.
I would expect that the auto zero (reading a zero input) should be done quite often, possible alternating between the signal and zero unless an AZ OP is used. JFET OPs tend to have quite some 1/f noise and thus a short time since AZ really helps. Thus is may be worth considering 20 ms integration - longer integration may not lead to lower noise. Even than the cycle is allready quite long: 20 ms integrate, 60 ms for disintegrate and a few ms for the capacitor discharge.