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Dual slope ADC improvement
namster:
Hi All,
I try to design a 4 or 5 digit ADC, I chose for this a Dual slope Topology which have the advantage of high resolution and low sampling frequency, the schematic in attachments is the first version, but it doesn't give a probate result, I estimated the resolution about 2 digit 1/2 for full scale of 2.5V the resolution was about 100mV, the ADC is controller by a PIC24FJ which is clocked by internal RC with PLL loop that give a frequency of 32Mhz, the timers have a resolution of 16bits, how can I improve the resolution?
duak:
Is the Z switch of U20 supposed to reset the Integrator formed by U19B? I see an unexpected connection of the -15V supply and U19B output.
Where are VCC & GND of U20 connected?
The LM311 comparator U21 has an open collector output. The pullup resistor R35 can introduce uncertainty when it is too large. I would try reducing it to 4K7 or even lower - the data sheet shows values of 500R to 1K0.
Kleinstein:
The zener diode D6 is a problem: Zeners tend to already leak well before there nominal voltage. This would cause nonlinear response.
The input resistor R23 is rather small with 1 K. The switch resistor can be on the order of 100 Ohms and temperature depended and also slightly nonlinear. So for the HC4053 switch I would consider some 20 K as the lower useful limit, maybe 5-10 K if there is compensation from the input and reference.
Using a much lower resistor for the input than for the references is more like a problem than really helping. It shortens the integration time, but causes problems: for mains hum suppression the integration time should ideally be 20 ms or a multiple of that. The rundown phase should ideally not be much longer, as the FET OPs in the integrator have quite some 1/f noise. For 20 ms chances are the integration cap would need to be larger.
Normally dual slope uses the same resistor for integration and the reference - so one part less that needs very precise.
The way 1/3 of the 4053 is used to reset the integrator, the voltage range of the integrator is rather limited.
Using the switches in a current steering mode, sending the current to ground or the integrator allows to use the 4053 switches even for higher signal and reference voltages. As there is already a +-15 V supply, I would prefer to have the ADC with something like a +-10 V (or just 10 V) input range. This makes the OP noise less critical.
For just a 4-5 digit target there is no real need for 2 OP integrator, just 1 OP should be good enough. In the current form the divider R31/R32 is way off, which makes the integrator slow to settle at the input. If using the 2 nd OP at all the right divider would be more like 1 K and 10K.
For the µC the internal RC clock may not be that good. Also the PLL may add some jitter - though maybe no that relevant at the target level. Anyway it is relatively easy to use a direct crystal clock for the µC.
A dual slope implementation without major flaws with the given OPs / switches should be capable to get about 4-5 digit resolution, more gets increasingly difficult. The limit should not be due to the timer resolution but is more due to effects like OP offset drift, noise and dielectric absorption in the integration cap.
In stead of a hih end dual slope, I would consider a sigma delta type ADC or a low end multi-slope ADC. It needs more complicated software, but avoid the DA limit.
P.S. Just saw the 50 K resistor between the switch and the integrator: so the resistor is not too small and essentially the same resistance is used.
iMo:
--- Quote from: Kleinstein on September 20, 2019, 04:34:08 pm ---
In stead of a hih end dual slope, I would consider a sigma delta type ADC or a low end multi-slope ADC. It needs more complicated software, but avoid the DA limit.
--- End quote ---
FYI - 6 pins ADS1110 does +/- 32768 counts (16bit), differential inputs +/- 2.048V, 1-8x PGA, 15-260 measurements/sec, I2C, internal 5ppm/C reference.
namster:
thanks All ,
@duak yes the Z siwtch is used to reset the integrator by shorting the capacitor , and yes the -15V is unexpected connection its surley a mistake , the VCC is conected to 5V out of U17 , the input will theorecly never exceed the 2.6V so normally it will not be a problem .
i used diffrents values of resistor and the value that i chose is 220 Ohm isn't too small
@Kleinstein
the zener Diode is used to limit the voltage at 2.6V , in my instrument in the case where no resistance to be measured is connected the voltage rise to 15V wich can damage the circuit i didn't find any other solution to correcte that , i am waiting for the Printed circuit board to do some test , for now i simulate the circuit with taking in consdieration all that everything you said .
@imo
I would have liked to use directly a Delta sigma ADC but isn't available in my country !
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