Dynamic Electronic Load Project

[Jay_Diddy_B]

Hi group,

A while a go I shared my design for a small electronic load that was limited to dc operation only. I am in the process of design and construction of a dynamic load. The dynamic load steps the load current so that the transient response of the power supply being tested can be observed.

I have decided to keep the design simple using readily available components. I have also focused on performance of the analog circuitry.

Features:

0-5A maximum continuous current
0-5A pulsed current at 330Hz

Maximum dissipation around 40W (There is no protection circuits in the design)

LTspice was used for circuit modelling. I have attached the LTspice model in a zip file attached to this post.

The prototype was constructed on a double-sided board made on an LPKF milling machine.

LTspice schematic:



LTspice results



Risetime:




Falltime:



Construction:


Real Schematic







Note: The MOSFETs will be bolted to a heatsink




Hardware Tests:

The current was measured with a Tektronix TCP202 current probe









I will post some additional pictures when I complete the mechanical part of this project.

Regards,

Jay_Diddy_B

 

[BravoV]

Thanks a lot JDB, I've been waiting for this kind of circuit for long time. 

YES !!! Finally, an affordable dynamic load circuit using just common jelly bean components ! 

Btw, is it true at the statement that any serious bench/lab power supply should be tested with "dynamic" load instead of just "static" load ?

Ok, now I'm going to observe & learn this circuit, and for sure I will come up with tons of noob questions to bug you  , hope you don't mind. 

Again, thank you. 

[Jay_Diddy_B]

BravoV,

A dynamic load can be used to generate a disturbance in a power supply's control loop.

The response to a step load change give an indication of a power supplies stability margins.

The Dynamic load is very easy and fast to use.

Serious power supply work in done with a Frequency Response Analyzer. This is a complicated and expensive piece of equipment that will display a Bode plot of the power supply's control loop. Hint: Google "Ridley Engineering",  "Venable Instruments" or "Omicron FRA"

Playing with the LTspice model is the best way to figure out how this circuit works.

Jay_Diddy_B

[dannyf]

"show some pictures for a user interface. This device needs to function for more than 20 years"

paintings or carvings, like those by ancient cavemen - they have survived millions of years.

[Jay_Diddy_B]

dannyf,

The user interface is two knobs. Knobs have been around for a hundred years and will still be current technology in the next 20 years. 

Jay_Diddy_B

[Jay_Diddy_B]

Hi,

I am going to share the ac analysis that was used to ensure that the electronic was stable.

LTspice model



The LTspice model includes a source inside the control loop. The source injects a disturbance into the loop. The signal is measured on either side of the source V(A) and V(B).

The .meas directives in the LTspice model is a network analyzer 

To see the Bode plot run the model in the normal way. The model will run 21 times, with different frequencies being injected into the loop.

After the last simulation is complete, click on the schematic, then click on View menu. Select SPICE error log. Right click in this window and select plot step'ed meas data. When asked 'Shall I write these as complex data?' click yes.
Right click in the new window, select add trace. Select gain from the list. This will display the Bode plot.




Damping Network R7 C2

The damping network R7 and C2 to compensate for the lead inductance to the power supply under test. If I remove the circuit by changing R7 from 2.2 Ohms to 2.2 MOhms:




Then I get the following result:



If I increase the Lead Inductance to a value greater than 1.8uH the circuit will oscillate.


If I add the damping circuit the circuit is stable.


I have attached a zip file with the LTspice model.

Regards,

Jay_Diddy_B

[BravoV]

JDB, few early questions and for sure more to come while I'm digesting this circuit. 

1. Why 330 Hz ? Is it because of your test at specific condition that you currently need ? What if that oscillator section is modded into adjustable frequency ? What range of the frequency sweep that is allowed without affecting the loop stability ?

2. If I replace the square wave oscillator say with wave gen that capable of producing various pulse shapes like sawtooth, triangle, shark fin, sine and etc, again, as above, will it affect the loop stability ?

3. I see you use two mosfets, what are needed to change/alter on the circuit if I use 4 mosfets (of course with it's own respective driver) ?

4. I have tons (bought from industrial surplus) National/TI LF411 jfet opamp, is it ok to use it instead of TL074 without the need to alter other components value, again, just worry about its stability, cause honestly I'm not very firm at gripping at how exactly to stabilize it yet, pardon, I'm still learning. 

5. Tried the simulation at your 1st circuit on ltspice, adjusted with lower offset and lower vref and I got this overshoot at the simulation, as you can see its almost at 100% more than the programmed current. Is this just at simulator ? or something else ? or just ignore it ? Check below pic.

[Jay_Diddy_B]

BravoV,

JDB, few early questions and for sure more to come while I'm digesting this circuit. 

1. Why 330 Hz ? Is it because of your test at specific condition that you currently need ? What if that oscillator section is modded into adjustable frequency ? What range of the frequency sweep that is allowed without affecting the loop stability ?

The reason 330Hz was chosen is that most power supplies have more than 1kHz of bandwidth. An optimized switching supply can have a bandwidth as high 125kHz. At 1kHz I wanted to be able to a couple of cycles. I then used resistors values and capacitors that I had.
When I am using my HP6060A load I normally select 100Hz or 1KHz.

2. If I replace the square wave oscillator say with wave gen that capable of producing various pulse shapes like sawtooth, triangle, shark fin, sine and etc, again, as above, will it affect the loop stability ?

The U3 -input (on the LTspice model) is a summing node. You can add the output from your signal generator, through a 100K resistor, to this input. You can then use all the waveforms in signal generator.

3. I see you use two mosfets, what are needed to change/alter on the circuit if I use 4 mosfets (of course with it's own respective driver) ?

You can use 4 MOSFETs, I just wanted to show more than one. I also wanted to limit my design to using a single quad op-amp. You just replicate the MOSFET, sense resistor, op-amp circuit. I would recommend 1 MOSFET for each 25W of dissipation. This arrangement forces the MOSFETs to share the current.

4. I have tons (bought from industrial surplus) National/TI LF411 jfet opamp, is it ok to use it instead of TL074 without the need to alter other components value, again, just worry about its stability, cause honestly I'm not very firm at gripping at how exactly to stabilize it yet, pardon, I'm still learning. 

The LF411 is fine. It has similar GBW and slew rate.

5. Tried the simulation at your 1st circuit on ltspice, adjusted with lower offset and lower vref and I got this overshoot at the simulation, as you can see its almost at 100% more than the programmed current. Is this just at simulator ? or something else ? or just ignore it ? Check below pic.

I haven't evaluated this fully, but I suspect it due the power supply sequencing in the model.

Jay_Diddy_B

[sorin]

I think that is something wrong with "dynamic load AC ANALYSIS.zip " please check it
when I run the stimulation the results are much different from yours
and don't have sense

[Jay_Diddy_B]

Sorin,

I have corrected the attachment in the original post.

There were two issues:

1) V2 should have been -0.1V instead of +0.1V

2) The 2.2Ohm 2.2uF damping network was missing.

The schematic shown are correct.

Thank you for pointing this out 

Jay Diddy_B

[BravoV]

JDB, thanks for the concise replies, really help me a lot. 

5. Tried the simulation at your 1st circuit on ltspice, adjusted with lower offset and lower vref and I got this overshoot at the simulation, as you can see its almost at 100% more than the programmed current. Is this just at simulator ? or something else ? or just ignore it ? Check below pic.

I haven't evaluated this fully, but I suspect it due the power supply sequencing in the model.

Looking forward to see the result after your evaluation. 

[Jay_Diddy_B]

BravoV,

The current overshoot that you observed is the damping network Capacitor being charged when the V3 is ramping up at the start of the simulation. This should not be a problem because the damping network is in parallel with the output capacitor of the power supply being tested.

The damping network is key to getting a large bandwidth.

It is damping a resonance that occurs between the output capacitance of the MOSFET and the lead inductance used to connect the load to the power supply under test.

Jay_Diddy_B

[BravoV]

The reason 330Hz was chosen is that most power supplies have more than 1kHz of bandwidth. An optimized switching supply can have a bandwidth as high 125kHz. At 1kHz I wanted to be able to a couple of cycles. I then used resistors values and capacitors that I had.
When I am using my HP6060A load I normally select 100Hz or 1KHz.

I'm not very sure about this, the switching supply bandwidth is not the same as switching frequency, right ?

The current overshoot that you observed is the damping network Capacitor being charged when the V3 is ramping up at the start of the simulation. This should not be a problem because the damping network is in parallel with the output capacitor of the power supply being tested.

Noted, and yes, I forgot the output cap of the V3 which is always there at every PSU, thanks.

[Jay_Diddy_B]

Hi,
I got some time this weekend to work on my Dynamic Load project. So here is an update.

The case that I am using is a aluminium extrusion. The case slots for mounting the board. I don't know who made the case because I reused one that I had found at a junk shop.

I made a new board  for the project. The changes were mainly mechanical. I added some Keystone 594K and 593K 9V battery holders. I also added 3mm to the length of the board, because I had forgot to include the dimension of the plastic molding around the front panel. I also adjusted the spacing of the BNC, pots and binding posts to fit the case. There is only just enough space on the front panel.


SMD side of the board:




Thru-hole side of the board:



Front Panel:



Here are some test results:



This image shows the current rise time. The upper trace is from the monitor port on the dynamic load. The lower trace is from a Tektronix TCP202 current probe.




This image shows the current fall time. The upper trace is from the monitor port on the dynamic load. The lower trace is from a Tektronix TCP202 current probe.




This image shows a few cycles of the current waveform. The upper trace is from the monitor port on the dynamic load. The lower trace is from a Tektronix TCP202 current probe.





For comparison here is the Tektronix TCP202 DC current probe monitoring a HP50501B in a 6050A mainframe, under the same conditions:




Regards,

Jay_Diddy_B

[BravoV]

Thanks for the update, the case looks beautiful and the results are identical with that current probe result.

Btw, abit nitpicking  on the two 9 volt batteries, are they secured only at it's terminal ?

Worry they may detached them self from the terminals if there is a hard bump on the case at the front, and somehow at worst case scenario the metal body of the battery shorted out the (+) terminal that is near behind it vs the screw head. A padding at the battery's bottom to push them firmly against those terminals maybe ? Just a thought.

[grenert]

The case that I am using is a aluminium extrusion. The case slots for mounting the board. I don't know who made the case because I reused one that I had found at a junk shop.

Very cool project, thanks for sharing it with us!
I think your case looks like a Hammond:
http://www.hammondmfg.com/1455V2.htm

[Jay_Diddy_B]

Hi,

I thought it might have been one of those Hammond cases, and I would have probably selected one, if I didn't find the surplus ones.

Here is a picture of the extrusion, the outside dimensions are 5.26 x 1.46 inches.



Here is a picture of the completed project.

Btw, abit nitpicking  on the two 9 volt batteries, are they secured only at it's terminal ?

Worry they may detached them self from the terminals if there is a hard bump on the case at the front, and somehow at worst case scenario the metal body of the battery shorted out the (+) terminal that is near behind it vs the screw head. A padding at the battery's bottom to push them firmly against those terminals maybe ? Just a thought.

I will probably put a little double-sided foam pad to secure the batteries. Good Idea !!

Jay_Diddy_B

[Dave Turner]

Nice and elegant. How do you determine the pot settings when using the unit?

[BravoV]

Start at lowest position while watching the scope, and slowly crank the pot up ?

[Jay_Diddy_B]

Hi group,

There has been a lot of interest in the forum on building constant current loads. One of the frequent questions that is asked is how do I stop my load from oscillating? or how do I choose the components around the op-amp to obtain stability. Other popular questions are how does the MOSFET gate capacitance impact my design.

I am going to share some analysis on a constant current load using LTspice. The analysis is done in the frequency domain. The goal is get reasonable bandwidth while being stable. For stability the phase shift has to be less than 180 degrees when the gain is greater than 1 (0dB). The loop bandwidth and phase margin are figures of merit for a control system.

Since the gain of a control loop is the product of the gains of the individual stages, we can build the control loop from the building blocks used in the circuit.

Power Stage

I could start by trying to model the power stage like this:



And I get the following result, which is useless:



The reason that the result is useless, is that the MOSFET has not been biased to the correct operating point.

The easy way to correct this is add an automatic Bias generator. This will servo the gate voltage to the correct operating point:




The result from this circuit are:




I can also reduce the MOSFET to a voltage controlled current source and its Gate-Drain and Gate-Source Capacitors:



If I model the correct values of transconductance, Crss and Ciss I get the same results. I do not need a bias circuit, because this model has no gate threshold voltage:



I now have a model that I can explore the effects of the gate capacitors directly. The DC gain is determined by the value of the source and the transconductance of the MOSFET. There is a pole formed by the gate resistor and input capacitance of the MOSFET.

Op-Amp Circuit

An op-amp is used to stabilize the load current. Typical this circuit it used:



The results show a single pole. It important that the op-amp has sufficient gain bandwidth product (GBW) so that the op-amp does not limit the bandwidth.



The circuit can also be reduced to this:



The results for this circuit are:




You can see that the real circuit, with the op-amp, has the same characteristics as the simplified model. The characteristics are determined by the resistor and the capacitor.

Open Loop Model

The two previous models can be placed in series to obtain the control loop response (oops!! replace R5 and L1 with a short  ):



The loop model response is:



This is great and the control loop is stable. What would happen if there is some inductance in the leads between the load and the power supply being tested?





The results indicates that the circuit is very close to oscillating. There is very little phase margin when the gain is 0dB. We could reduce the gain, but this would also reduce the bandwidth of the control loop.

We could add a damping circuit as shown in this model:



The result is:




The potential for oscillations resulting from inductance on the leads to the load has been significantly reduced.


Closed loop Modelling

The loop gain can be measured with the control loop closed, by placing the disturbance source in the feedback path. The signal can be measured on either side of the disturbance source to determine the loop gain.



The results of the closed loop model are:



To be continued....

Jay_Diddy_B

[Jay_Diddy_B]

Continuing...

Lead Inductance can be added to the closed loop model:



An the results are similar to the open loop model, the circuit is on the edge of oscillation:



An RC damping Circuit can be added to the model:



And the stability margins are restored:




I hope this analysis give some insights in to how to design a stable load.

May all your loads be stable !!

Regards,

Jay_Diddy_B

[BravoV]

May all your loads be stable !!

LOL, thanks for the updates.

As a noob, after reading these excellent additions, suddenly I feel like an expert now.   

[kt315]

Jay_Diddy_B,

Thanks a lot for putting in the effort to explain your analysis. It is by far the most clear explanation I've seen so far. It is the most useful explanation I have seen so far ...   

Could you explain in a bit more details please how you read the last two charts of your post. Specifically, how do you determine if the circuit is stable.

If I read it right, the unity gain of the loop is at 30 kHz. But in both cases (before and after dampening is added) the phase shift seems to be pretty far away from 180. 
Or do I read it wrong?

Thanks.

[Jay_Diddy_B]

Jay_Diddy_B,

Thanks a lot for putting in the effort to explain your analysis. It is by far the most clear explanation I've seen so far. It is the most useful explanation I have seen so far ...   

Could you explain in a bit more details please how you read the last two charts of your post. Specifically, how do you determine if the circuit is stable.

If I read it right, the unity gain of the loop is at 30 kHz. But in both cases (before and after dampening is added) the phase shift seems to be pretty far away from 180. 
Or do I read it wrong?

Thanks.

Hi,
 I have zoomed in on the area that we are interested in. Here is the results without the damping network:



I have used arrows to indicate the phase margin and the gain margin. The phase margin is a very good 84 degrees. The gain margin is low, only 3dB.

If I add the damping network. I get the following result:



I have the same phase margin 84 degrees, but the gain margin has increased to a massive 52dB.

So why is this problem? 

Both of these loops are stable. The issue is that part of the control loop, the transconductance of the MOSFET varies with the operating point. The gain increases as the current increases. If I modify my model to this:



Here I am stepping the load current from 0.5A to 5A. I get this result:



The high current result is unstable, the gain is 3dB when the phase angle is 0 degrees.

If I switch to the time domain. In this model I am ramping the load current from 0 - 5A:



I get this result:



You can see the control loop breaks into oscillation when the current is greater than 1.9A.
Note, that I had to add a little ripple, just 10mV, to disturb the control loop to get the oscillation to show up.

If I add the damping network I can sweep the current from 0-5A and there are no oscillation as predicted in the frequency domain. (There is nothing to see, so I have not included the results).

An alternative solution to the damping network, is to reduce the loop gain. If I increase the capacitor by factor 10, to 2200pF, I get this result:



This is a very stable system, but the limited bandwidth, would prevent the circuit being useful for transient load tests.

Regards,

Jay_Diddy_B

[kt315]

You are my hero. Thanks a lot.