Easiest way to divide 10MHz to 1MHz?

[TERRA Operative]

I have a few Tektronix TM500 modules that require a stable 1MHz frequency source for testing and calibration.

I have a few 10MHz OCXO's here, but nothing in 1MHz. Does anyone have any suggestions to easily divide 10MHz down to 1MHz?
Is this something easy to build or is an ebay module the easiest thing to use?

[pqass]

See last schematic here: http://amateurtele.com/index.php?artikel=221
At 5V a 74HC390 has a fmax=55MHz, at 2V it has a fmax=20MHz.  So it should handle any Vcc you may have.
At 5V a 74LS390 has a fmax=35Mhz for standard TTL.

https://assets.nexperia.com/documents/data-sheet/74HC_HCT390.pdf
https://www.ti.com/lit/gpn/sn54ls393-sp

[Gyro]

If you want to maintain a 1:1 mark/space on the output, then you need to connect it so that the divide by 5 stage is followed by the divide by 2 stage.

A divide by 10 only requires one half of the 74xx390. You could use a 74xx90 instead, although they seem to be a bit less common these days. You can use the other half of the 390 to provide another divide by 10, or 2, or 5 (not 1:1).

[Ian.M]

Single CMOS D type flipflop with a RC delay  between /Q and D so it divides by ten at or near 10MHz in, not by two.  With symmetrical logic thresholds the duty cycle is inherently 50%.   The two nearest division ratios it can lock to are 8:1 and 12:1, 1.25MHz and 833Khz respectively so its easy enough to measure that and trim the R to the midpoint between the two extremes where it looses its 10:1 lock.  You can probably build it and trim it in less time than it takes to find  a suitable divider you can order!

[bson]

For an actual 1MHz oscillator rather than a clock, the best easiest is probably phase-locking a VCO to the 10MHz reference XO.

[pqass]

If you want to maintain a 1:1 mark/space on the output, then you need to connect it so that the divide by 5 stage is followed by the divide by 2 stage.

Isn't the order irrelevant since going through the first flip-flop automatically gives you a 50% mark/space since a state transition is only triggered on the same falling (or leading) edge of the clock; not both edges.     See attached.

EDIT: While the above is true, it becomes false after the 2nd and 3rd flip-flop.  See my post later in this thread.

Also, one should probably add a buffer with schmitt trigger input (like 74HC14 or 74HC132) to square-up the incoming 10MHz.

Of course, I'm assuming here a square wave output is all that's required.  Is a sine wave absolutely needed to feed the Tektronix TM500 modules?

[Benta]

For an actual 1MHz oscillator rather than a clock, the best easiest is probably phase-locking a VCO to the 10MHz reference XO.

Why on earth would you introduce a PLL, when a simple divide circuit can do the job? A /10 divider with a 1:1 mark space, aka, 50% duty cycle, is the easiest job in the world.
Gyro's suggestion of a /5, /2 counter is spot on.

[Benta]

Isn't the order irrelevant since going through the first flip-flop automatically gives you a 50% mark/space since a state transition is only triggered on the same falling (or leading) edge of the clock; not both edges.

I think you need to re-read "Digital counters 101". Counter output is normally just one clock cycle wide. Dividing the output by 2 brings 50% DC.

[bdunham7]

I don't know what you have for equipment, but if this is a one-time thing just for testing and not something continually used, I would connect the OCXO to the external reference input of my AWG or RF Generator and set it for a 1MHz output. 

[bd139]

+1 for a 74HC390 here. Or two 74LS90's

[pqass]

Isn't the order irrelevant since going through the first flip-flop automatically gives you a 50% mark/space since a state transition is only triggered on the same falling (or leading) edge of the clock; not both edges.

I think you need to re-read "Digital counters 101". Counter output is normally just one clock cycle wide. Dividing the output by 2 brings 50% DC.

I take it back; the order of the divide-by-2 vs divide-by-5 parts of the 74HC390 is relevant. First divide-by-5 then divide-by-2 as per the schematic that I referenced in my first post.

The reason is that the divide-by-5 part cycles the outputs Q3..Q1 from LLL to HLL (0..4 decimal). If you're to pick off the output at Q3, that gives 4 Ls and 1 H (after 5 clocks); that's not 50% mark/space.  Now feeding this Q3 to CP0 (the divide-by-2 part), this will do as I said, turn any input not at 50% duty into an output (Q0) at half the frequency and also at 50% duty cycle (since it transitions on only 1 edge).

[5065AGuru]

You might want to consider the picDIV dividers!

8pin DIP or SOIC, provide power, input, and you get your output!

http://www.leapsecond.com/pic/picdiv.htm

The closest one is the pd02 which divides by 100.

pd02.asm:;   PD02 -- PIC "4-pin" 10^2 frequency divider (10 MHz to 100 kHz)

Full list here: http://www.leapsecond.com/pic/picdiv-list.htm

You could maybe contact Tom Van Baak and see if a divide by 10 would work.

tvb@LeapSecond.com

Cheers,

Corby

[Ian.M]

It wouldn't as the 8 bit PICs he uses take four clock cycles per instruction and everything is locked to that ratio.   The only way of getting round that would be to port his concept to a newer 8 bit chip that has an internal 4x PLL multiplier for the clock, which allows it to execute one instruction per external clock.  You'd then set up Timer 2 for a period of 10 instruction cycles and set up a PWM module for 50% duty cycle, at which point you've just done the job of the proposed 74xx390 with several times the jitter and cost.

You could also get there by injection locking a classic two transistor astable multivibrator, using a pullup resistor and a third transistor as a saturated switch for the output.

[vk6zgo]

I would suggest a 4017, except I'm not sure if it would operate at 10MHz.
Maybe you could find something similar, with an adequate frequency range, rather than get tied down with combinations of other division ratios.

The Drake SSR1 radio used a 10MHz xtal osc, divided  down  to 1MHz.
From memory, it used a single device, but not a 4017.

[BrianHG]

I would suggest a 4017, except I'm not sure if it would operate at 10MHz.
Maybe you could find something similar, with an adequate frequency range, rather than get tied down with combinations of other division ratios.

The Drake SSR1 radio used a 10MHz xtal osc, divided  down  to 1MHz.
From memory, it used a single device, but not a 4017.

Well, you better believe that the 74HC4017 will reach the 10Mhz mark...
In fact, we are talking 30MHz at 5v.
It will even do 10MHz at 2.5v.
And its readily available everywhere...

[TERRA Operative]

Awesome info, thanks all!
It looks like the 74xx390 is the go, simple to use and it just so happens that I have a tube of 25 of HD74HC390P, so I think I'm set.

Who says hoarding old parts never comes in handy!   

[David Hess]

For an actual 1MHz oscillator rather than a clock, the best easiest is probably phase-locking a VCO to the 10MHz reference XO.

Why on earth would you introduce a PLL, when a simple divide circuit can do the job? A /10 divider with a 1:1 mark space, aka, 50% duty cycle, is the easiest job in the world.  Gyro's suggestion of a /5, /2 counter is spot on.

Why would you introduce a counter, when a simple single transistor 1 MHz oscillator can be injection locked to the 10 MHz source?  An injection locked oscillator is the easiest job in the solar system.

[TERRA Operative]

Well I had a poke around with a schematic just now, taking ideas from here and there. I thought I'd give myself some options on output frequency.

Should I be terminating the input maybe? Let me know if there are any glaring mistakes or omissions. 

[David Hess]

Should I be terminating the input maybe? Let me know if there are any glaring mistakes or omissions. 

At 10 MHz, a termination should not be required unless your patch cables are really really long, and really not even then if source termination is used unless the cable is more than point-to-point.

74HC390 counters are a good way to go for this.  Why make things more complicated?    I do not see any obvious mistakes.

In a high performance design, I would optimize for low phase noise and some kind of universal driver for the outputs.

[pqass]

Well I had a poke around with a schematic just now, taking ideas from here and there. I thought I'd give myself some options on output frequency.

Should I be terminating the input maybe? Let me know if there are any glaring mistakes or omissions. 

U1.4 and U1.3 outputs should be 1MHz and 5MHz, respectively. 
U2.2 is a divide-by-5 into a divide-by-2 whereas U2.1 is just a divide-by-2.

[magic]

For smallest solution, use any DIP8/SO8/SOT3-6 microcontroller with clock input pin and PWM

[Ian.M]

No.  Not *any*.  See my comments in reply 12 above.  The PWM clock has to be taken direct from the input clock  to be able to get the right frequency at 50% duty cycle.  Older low pin count PICs don't support that.

[eblc1388]

With an ATMega8 microprocessor, one can obtain 5MHz and 1MHz by CTC on Timer1 and Timer2 output respectively. This is a hardware solution and operates without software support after setting up.

Then with a bit of creative programming of cycle counting, it is then possible to obtain 100KHz, 10KHz, ...0.01Hz simultaneously on the 8-bit PORTD pins. All with 50% duty cycle.

A true one chip solution. 

[TERRA Operative]

How accurate is that? Enough for using as a reference for calibrating test gear?

[Benta]

Suggesting a "solution" needing software development (not a lot), a programming and debugging environment, programming/burning hardware etc. instead of just buying a 25 cent part with far superior timing characteristics (74HC390) and just using it 'as is' is "better"?

Wow. I see parallel universes that seem to consist of pull-down menus, PIC and ATMega brainwash.

If those contributors worked with me, they'd be fired on the spot. Just throwing any 8-pin MCU at any problem is not engineering to me.

Sorry, had to get that off my chest.