Electronic Load MOSFET balancing

[Jay_Diddy_B]

Hi,

Here is another paper on MOSFET thermal instability:

http://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/20100014777.pdf

This all started when people noticed that MOSFETs were failing inside their published SOA curves. What happened was the MOSFETs designers were so focused on improving the switching performance and RDSon that they forgot that there are some applications that use the MOSFETs in the linear region.

Older parts generally do better in these, linear, applications. The problem is that not all the datasheets have reliable SOA graphs. If the graph looks like the IRFP3306 that I posted early then it is probably reliable. If the graph consist of straight lines, it from the results of calculations and may not include the thermal instability region.

This is the SOA curve from the Vishay IRFP250. This is probably based on calculation, not measurement. The limitation is based on transient thermal impedance only. It is an example of an unreliable SOA curve.:



Regards,

Jay_Diddy_B

[DanielS]

My application requires some of the total equivalent resistance to be around 150 mohms.

Rds(on) has no meaning for linear applications.

It does enable you to summarily dismiss FETs which have higher ON-resistance than what your linear application requires - you are not going to use FETs with 1 ohm ON resistance in an electronic load that needs to go below 0.1 ohm... unless you want to put 10+ of 'em in parallel.

I would say this just about as useful as voltage and current for weeding out the initial device selection for applications where the FETs may need to operate just shy from their ON-region.

[Kevin.D]

With regards to mosfet selection and RDS(on) advice ,
It's true to say having a low RDS(on) does not have any meaning in linear mode,
Though It does play a small role here (e.Load) in that it will determine the minimum resistance that the load can achieve ( minimum Burden Resistance), this then determines the maximum current the load could sink with low input Voltages present. (simple e.g - if we have a Rsense of .1 ohm and a RDS(on) of .1 ohm then the Max current we could possibly sink when input is only 500mV would be .5/.2= 2.5 A  ,if you have two of these in parrallel then it would be 5A ).

But also when choosing a Mosfet for linear application I would use RDS(on) a filter search critera and choose the power mosfet with the HIGHEST rds(on) I could accomodate to meet my minimum resistance critera.
 The logic here is that the newer generations of mosfet which have been optimised for switching (so optimised for a really Low RDS(on) and high GM which is good for switch efficiency but not meaningfull for linear operation ,and one of the trade offs (no free lunch as usual) for producing a low RDS(on) high transconductance Fet seems to be that the Vgs Zero temp Co  'ZTC point' (which is the point which if we are below we have to have some extra thermal derating at higher Vds) gets even higher so  requiring us to have extra derating .
I am not 100% sure why the ZTC point moves up so much with lower rds(on) power mosfets but it will make a large difference to power handling at higher end of Vds .
By selecting an older generation or even newer but unoptimised RDS(on) FET that should be giving you a mosfet with higher ZTC point and so will have much less of this extra thermal derating..
So filtering by this critea and power dissipation should be a good selection method for this application, no need for expensive ones as the real bottle neck here in this application  is Case to Sink Thermal resitance , so if theres no  need to skimp on numbers you can use as many cases as required in parrallel to get overall low Case to Sink thermal resistance,
also as Mr J.Diddy pointed out opamps are also really cheap  so giving each it's own opamp is no big cost.(drive speed is also another reason why it's also beneficial to have each mosfet with it's own opamp for the extra drive current capability you are getting over having one opamp trying to drive multiple large Fets).

 (I did A quick fet search which turns up examples like the IRFP250 which is only $1.50 a piece and will be much more suitable than your irfp3306 (notice  the much higher RDS(on) 85mO compared to the irfp3306 with 6mO and notice there is much less extra derating required on the soa at the right bottom corner ,this one is used in Maynuo load, someone said ) .
 Also to add another reason for choosing a higher RDS(on) power fet for linear mode operation is that there's also  a realtionship between Crss (gate to drain capacitance- Cgd) and RDS(on) . Cgd generally gets larger the lower the RDS(On) is made, and  having as little Cgd as possible is important for a stable and fast controll loop, in this application it's value is multiplied (miller effect and low Vds effect) and can appear as much as 1000 times larger as the figure given in the mosfet data sheets. This capacitance has to  be  dis/charged by the driving opamp so it's best if this is kept small.

Regards

[dannyf]

Vgs Zero temp Co  'ZTC point'

It is structural. Lateral mosfets have its transition points in the 1-200ma range, and vertical mosfets have its transition points typically in the 10 - 20amp range -> for linear applications, the mosfets are destroyed far before you even reach that kind of levels.

[diyaudio]

With regards to mosfet selection and RDS(on) advice ,
It's true to say having a low RDS(on) does not have any meaning in linear mode,
Though It does play a small role here (e.Load) in that it will determine the minimum resistance that the load can achieve ( minimum Burden Resistance), this then determines the maximum current the load could sink with low input Voltages present. (simple e.g - if we have a Rsense of .1 ohm and a RDS(on) of .1 ohm then the Max current we could possibly sink when input is only 500mV would be .5/.2= 2.5 A  ,if you have two of these in parrallel then it would be 5A ).

But also when choosing a Mosfet for linear application I would use RDS(on) a filter search critera and choose the power mosfet with the HIGHEST rds(on) I could accomodate to meet my minimum resistance critera.
 The logic here is that the newer generations of mosfet which have been optimised for switching (so optimised for a really Low RDS(on) and high GM which is good for switch efficiency but not meaningfull for linear operation ,and one of the trade offs (no free lunch as usual) for producing a low RDS(on) high transconductance Fet seems to be that the Vgs Zero temp Co  'ZTC point' (which is the point which if we are below we have to have some extra thermal derating at higher Vds) gets even higher so  requiring us to have extra derating .
I am not 100% sure why the ZTC point moves up so much with lower rds(on) power mosfets but it will make a large difference to power handling at higher end of Vds .
By selecting an older generation or even newer but unoptimised RDS(on) FET that should be giving you a mosfet with higher ZTC point and so will have much less of this extra thermal derating..
So filtering by this critea and power dissipation should be a good selection method for this application, no need for expensive ones as the real bottle neck here in this application  is Case to Sink Thermal resitance , so if theres no  need to skimp on numbers you can use as many cases as required in parrallel to get overall low Case to Sink thermal resistance,
also as Mr J.Diddy pointed out opamps are also really cheap  so giving each it's own opamp is no big cost.(drive speed is also another reason why it's also beneficial to have each mosfet with it's own opamp for the extra drive current capability you are getting over having one opamp trying to drive multiple large Fets).

 (I did A quick fet search which turns up examples like the IRFP250 which is only $1.50 a piece and will be much more suitable than your irfp3306 (notice  the much higher RDS(on) 85mO compared to the irfp3306 with 6mO and notice there is much less extra derating required on the soa at the right bottom corner ,this one is used in Maynuo load, someone said ) .
 Also to add another reason for choosing a higher RDS(on) power fet for linear mode operation is that there's also  a realtionship between Crss (gate to drain capacitance- Cgd) and RDS(on) . Cgd generally gets larger the lower the RDS(On) is made, and  having as little Cgd as possible is important for a stable and fast controll loop, in this application it's value is multiplied (miller effect and low Vds effect) and can appear as much as 1000 times larger as the figure given in the mosfet data sheets. This capacitance has to  be  dis/charged by the driving opamp so it's best if this is kept small.

Regards

Yup, Kevin is on the money, fully agree!

One issue though that wasn't covered is the Qg parameter of the mosfet "gate capacitance channel" and how an operation amplifier deals with driving capacitive loads that may lead to phase shift resulting in self sustained oscillation (feedback from the current sense node) formed by the pole/zero location which is the product of the parasitic gate charge and output impedance of the op-amp forming a RC lag.

I recommend this video by Matt Duff, he did a full short series on op-amp stability, one video specifically covering driving capacitative loads.