Measuring PCB trace capacitance

[Mark]

What is a valid method to measure trace capacitance on a multi-layer PCB? 

I have an 8-layer backplane:

TOP = signals
I2 = GND
I3 = 18V (from which the 3V3 is derived)
I4 = GND
I5 = I2C bus
I6 = 18V
I7 = signals
BOTTOM = GND

I am trying to measure the I2C bus capacitance so that I can calculate the maximum pull-up resistor value.  The I2C bus has pull-ups to 3V3 and the 3V3 is derived from the 18V supply. 
I have simply removed the board from the system and measured the capacitance between SCL and GND and between SDA and GND.  An Analog Discovery and a DE-5000 LCR meter both agreed on 115pF. 

Is this a valid measurement, or should the 18V plane be connected to GND for the measurement?  My worry is that the I2C is sandwiched between GND and 18V planes and the 18V plane would normally have a low impedance to GND, so omitting it from the measurement would yield an inaccurate result. 
Should I connect 18V to GND for the trace capacitance measurement? 

[CosteC]

If your board has all capacitors soldered, your 18 V plane is capacitivly connected to GND already, so extra connection does not seem needed.
Do you measure with ICs soldered or not? IC inputs have capacitance of thier own. This capacitance is dependent on if ICs are powered or not.

Another interesting question is at what frequency you measured capacitance with DE-5000? 100 Hz or 100 kHz

Design question: if you measured 115 pF, for what capacitance you will calculate pull-ups? In my opinion, calculating pull-ups for 115 pF is very risky option.

[drkntz]

Yeah, your 18V plane is an AC ground, and would factor into your capacitance calculation. You could measure between 18 and your serial lines and add that to your 115pF measurement. 115pF sounds high to me, how long are your traces?

What data rate is your I2C bus? Is this level of analysis really necessary? I would typically just pick something in the 3.3-10k ohm range and if I'm really worried about it I would check the rise time on the prototype.

[Mark]

Thanks for the responses,

There are no capacitors on this backplane, or any other components between 18V and GND.  The 18V comes from a PS that plugs into the backplane. 

The traces are approx 50cm (19"). 
Measurements with DER DE-5000 were at 100Khz, but Analog Discovery capacitance result is quite flat over a 100Hz to 2MHz range. 

There are plug-in other boards in the system that will obviously change the capacitance if they are installed or not, but the main bus capacitance is due to this backplane and I wanted to isolate this board and make valid measurements of this backplane on its own. 

I can also use the rise time technique to verify the measurements. 

[Doctorandus_P]

You can use "too weak" pullups and/or just stretch the X-axis on your oscilloscope and back calculate the capacitance from the RC time.
Seeing the I2C signals on an oscilloscope and verifying timing and signal levels should always be a part of the I2C verification anyway.

[CosteC]

Thanks for the responses,

There are no capacitors on this backplane, or any other components between 18V and GND.  The 18V comes from a PS that plugs into the backplane. 

The traces are approx 50cm (19"). 

I dare to not believe: if you step down 18 V down to 3.3 V then you shall HAVE some components between 18 V and GND (unless 18 V has separate return and there is isolated 18V->3.3V PSU)

Did you measured capacitance on fully assembled board? With all ICs, caps etc.

[T3sl4co1l]

Unrelated comment: are you sure 18V plane is a good idea?  (Implying: whole board, or at least overlapping a significant number of traces on adjacent signal routing layers; evidently, I2C at the very least.)  Higher voltages tend to be noisier (power distribution, lots of converters?).  Maybe it's well enough filtered and this isn't a problem -- you've already solved these considerations -- but it suggests a potential alternate solution using less filtering (noisier rail), saving on component cost and space.  If it goes to an external connection, a local LC filter would likely do more [filtering] with fewer components.

Obviously, I don't know anything else about this, and the board's already been fabbed; just putting this out there in case the considerations / alternatives / tradeoffs are relevant in the future.

Tim

[Mark]

Thanks for the responses,

There are no capacitors on this backplane, or any other components between 18V and GND.  The 18V comes from a PS that plugs into the backplane. 

The traces are approx 50cm (19"). 

I dare to not believe: if you step down 18 V down to 3.3 V then you shall HAVE some components between 18 V and GND (unless 18 V has separate return and there is isolated 18V->3.3V PSU)

Did you measured capacitance on fully assembled board? With all ICs, caps etc.

This is just a backplane for distributing the 18V and other signals between plug-in modules (including the 18V power supply). 
There are only connectors for the plug-in modules, no other components on this backplane.  No decoupling either! 
A 3.3V supply is generated from the 18V on each plug-in module. 
The board measures 2" x 16" and has the I2C bus sandwiched between flooded planes for GND and 18V. 

I4 = GND
I5 = I2C bus
I6 = 18V

The purpose of this exercise is to learn how to measure the capacitance of the I2C bus for this board in some valid way. 
After all, the standard sets a limit of 400pF and TI's app note shows how to calculate the pullup resistor values based on bus capacitance. 
https://www.ti.com/lit/an/slva689/slva689.pdf
Sure Cbus can be estimated from the PCB stackup (with possibly wildly inaccurate results), and can be calculated from the rise time for the whole system, but there must be an easy(?) method to measure it on such a simple board? 

Using the DER DE-5000 LCR meter (test freq = 100kHz) I get these results:
SCL to GND = 115pF
SCL to 18V = 115pF
SCL to (GND+18V tied) = 116pF
GND to 18V = 6.3nF

Unrelated comment: are you sure 18V plane is a good idea?  (Implying: whole board, or at least overlapping a significant number of traces on adjacent signal routing layers; evidently, I2C at the very least.)  Higher voltages tend to be noisier (power distribution, lots of converters?).  Maybe it's well enough filtered and this isn't a problem -- you've already solved these considerations -- but it suggests a potential alternate solution using less filtering (noisier rail), saving on component cost and space.  If it goes to an external connection, a local LC filter would likely do more [filtering] with fewer components.

Obviously, I don't know anything else about this, and the board's already been fabbed; just putting this out there in case the considerations / alternatives / tradeoffs are relevant in the future.

Tim

18V is what I'm stuck with.  It is distributed to 10 modules and each module has multiple DC-DC converters for 5V, 3.3V, 1.5V, 1.2V, 1.1V.  The decision was made to keep the backplane simple, so maybe that is why there is no decoupling apart from plane-plane capacitance! 

[Mark]

You can use "too weak" pullups and/or just stretch the X-axis on your oscilloscope and back calculate the capacitance from the RC time.
Seeing the I2C signals on an oscilloscope and verifying timing and signal levels should always be a part of the I2C verification anyway.

I checked a partial system this way, (one master module, one slave module and the backplane). 
I have a variable R on both SCL and SDA for test purposes. 
With Rpullup = 10.73k, I used the charging capacitor equation
ν = V(1 - e^(-t/RC))

V – source voltage
ν – instantaneous voltage
C– capacitance
R – resistance
t– time

Assuming V = 3.3V
v measured at 1.322V
t measured at 1.268usec
therefore C = 230pF. 

Using the equations from the TI app note linked previously, it suggests that Rp(max) = 1.533k. 
I then adjusted the variable resistor until I got to the risetime of 300ns (the I2C standard specifies this as a maximum). 
VIL = (0.3 x 3.3V) = 0.99V
VIH = (0.7 x 3.3V) = 2.31V. 
Risetime = tr = between VIL and VIH. 
X1 X2 cursors are 300ns apart. 




Y1, Y2 match up with the VIL VIH values calculated above and (Lo & behold) the variable pull-up resistance was measured at 1.59k, not far off the TI app note calculated value. 

[wasedadoc]

Lots of good info, including calculation of pull up resistor in https://www.ti.com/lit/pdf/sbaa565#:~:text=1.1%20History&text=I2C%20was%20developed%20in%201982,converters%20and%20other%20peripheral%20devices.

[Doctorandus_P]

Unrelated comment: are you sure 18V plane is a good idea? 

That is a good question, that needs some consideration.
In general having two GND planes (on a 4-layer PCB) is considered better then a GND plane and a power plane. It's especially the thin prepreg layer that improves coupling compared to the thick inner core. "Power" can be routed as tracks that can handle the current with a low enough voltage drop, but do of course need local decoupling for IC's. You may want to do some research in this area.

[T3sl4co1l]

Using the DER DE-5000 LCR meter (test freq = 100kHz) I get these results:
SCL to GND = 115pF
SCL to 18V = 115pF
SCL to (GND+18V tied) = 116pF
GND to 18V = 6.3nF

Draw a delta of capacitors.  Set one to 6.3nF.  Set the other two to 58pF.

Repeat for SDA, drawing another pair of 58pFs from the 6.3nF to it.

And, possibly draw an additional capacitor between SCL and SDA, the value of which will be pretty small.  Ideally a transfer capacitance measurement would be made, i.e. one electrode excited with AC with respect to surrounding grounds (planes, tied), AC current measured on the other electrode.

C_{SCL-SDA} will be small, because the capacitance to planes dominates.  If they're minimum spaced, it's probably on the order of 1/10th or 6pF.

Note that you need to add the sum total of all attached cards to get the bus capacitance.  If those can be measured separately, then this is easily solved for.

That is a good question, that needs some consideration.
In general having two GND planes (on a 4-layer PCB) is considered better then a GND plane and a power plane. It's especially the thin prepreg layer that improves coupling compared to the thick inner core. "Power" can be routed as tracks that can handle the current with a low enough voltage drop, but do of course need local decoupling for IC's. You may want to do some research in this area.

The main thing here is that it needs less than... 0.3V maybe, of induced noise?  I2C has very little noise immunity, and this is intentional by design.  Logic power planes normally have some 10s of mV if that, so make excellent reference planes; the same level out of 18V though is another about 16dB lower ripple fraction, much more strict, and worth emphasizing.

Anyway, that's all I wanted to do, highlight that concern, not make a discussion out of it.

Tim

[Mark]

C_{SCL-SDA} was measured at... 60pF
That's because the traces on the backplane that are being used for I2C were originally routed as a differential pair. 
I can see significant crosstalk:

[T3sl4co1l]

No, draw it out; you're measuring mostly (SCL to GND+18V) in series with (SDA to GND+18V).

In fact since each is 116pF and half of that would be 58pF but the measurement is 60, the additional 2pF should be strictly SCL to SDA.

Tim

[Terry Bites]

This cute ic solved my fluid sensing problems in under a minute: FDC1004 from TI is a $5 wonder. You can get some hackable code from here www.ti.com/tool/download/SNVC187
I played with it for days before getting back to the actual job. So much fun!
I got an eval board as a freebie, its $200 now, that seems a bit steep. Oh well, thats evals for you.

www.aliexpress.com/item/1005004643706965.html?spm=a2g0o.productlist.main.23.53af9bfbMZTpB7&algo_pvid=934954af-6a0c-422e-970b-8f4910e44d5c&algo_exp_id=934954af-6a0c-422e-970b-8f4910e44d5c-11&pdp_npi=4%40dis%21GBP%2164.54%2164.54%21%21%2180.00%21%21%40211b88ef16924565671395439edab7%2112000029953860995%21sea%21UK%210%21A&curPageLogUid=lqyKgIZxpaHT