One could read many times how important it is if one wants to pass EMC and similar certifications to do in-house testing at all stages of testing. Unfortunately I haven’t been able to do that and now I’m looking at what can be done with what I have. I have already opened a couple of topics (
link,
link) on the topic of EM compatibility, and this is a new one.
On my last visit to an accredited lab, I passed a test for conducted emission for BB3. However, a new problem has arisen related to radiated emission. In fact it had been there from the beginning only that no measurements had been made before to indicate that.
There was a very pronounced interference on 108 MHz and the surrounding frequencies that I did not know at first where it came from.
I thought I would have to get a broadband antenna and make some test chamber to reproduce the problem, but it turned out to be very easy to catch if probed in the right place. In this case it was the RESET pin on the output connector of the MCU module! Probably this is no coincidence because RESET is tied with a pull-up to the +Vdd MCU.
If measured with an x10 probe on a 70 MHz oscilloscope it looks like this:

SA shows a pronounced 108 MHz but also several higher harmonics:

The first thing that came to my mind was that the problem was related to the dubious power supply of the MCU. For I no longer remember what reason I decided to power the MCU from a single point leading to a power plane (+Vdd) that is separate from the rest of the +3.3 V located on layer 3 of the PCB. It currently looks like this:

Yes, layer 3 is anything but optimal. Yesterday I immediately got to work and modified it to get as uniform as possible +3.3 V:

However yesterday I still didn’t know where those 108 MHz came from (the system clock is 216 MHz obtained by a prescaler from an external 25 MHz XTAL). Now I think this is related to SDRAM whose clock is set to twice smaller than the system, i.e. 108 MHz. When we lowered it to a third of the system clock, 72 MHz (and associated higher harmonics) appeared instead of 108 MHz.
This assumption is further confirmed by the test when we turned off SDRAM and switched the frame buffer to system RAM. Then the oscilloscope gives the following:

... or SA shows this:

The question is whether intervention on layer 3 is sufficient and what more could be done without switching from 4-layer to 6-layer PCB which I would like to avoid if at all possible. I see that ST's evaluation boards are made in 6 layers, I would like to believe that this is not a requirement for passing EMC tests.
Below is a picture of the point where I measure the massive ripple (RESET output):
