EMI issue with bad power plane and SDRAM

[prasimix]

One could read many times how important it is if one wants to pass EMC and similar certifications to do in-house testing at all stages of testing. Unfortunately I haven’t been able to do that and now I’m looking at what can be done with what I have. I have already opened a couple of topics (link, link) on the topic of EM compatibility, and this is a new one.
On my last visit to an accredited lab, I passed a test for conducted emission for BB3. However, a new problem has arisen related to radiated emission. In fact it had been there from the beginning only that no measurements had been made before to indicate that.
There was a very pronounced interference on 108 MHz and the surrounding frequencies that I did not know at first where it came from.
I thought I would have to get a broadband antenna and make some test chamber to reproduce the problem, but it turned out to be very easy to catch if probed in the right place. In this case it was the RESET pin on the output connector of the MCU module! Probably this is no coincidence because RESET is tied with a pull-up to the +Vdd MCU.
If measured with an x10 probe on a 70 MHz oscilloscope it looks like this:



SA shows a pronounced 108 MHz but also several higher harmonics:



The first thing that came to my mind was that the problem was related to the dubious power supply of the MCU. For I no longer remember what reason I decided to power the MCU from a single point leading to a power plane (+Vdd) that is separate from the rest of the +3.3 V located on layer 3 of the PCB. It currently looks like this:



Yes, layer 3 is anything but optimal. Yesterday I immediately got to work and modified it to get as uniform as possible +3.3 V:



However yesterday I still didn’t know where those 108 MHz came from (the system clock is 216 MHz obtained by a prescaler from an external 25 MHz XTAL). Now I think this is related to SDRAM whose clock is set to twice smaller than the system, i.e. 108 MHz. When we lowered it to a third of the system clock, 72 MHz (and associated higher harmonics) appeared instead of 108 MHz.

This assumption is further confirmed by the test when we turned off SDRAM and switched the frame buffer to system RAM. Then the oscilloscope gives the following:



... or SA shows this:



The question is whether intervention on layer 3 is sufficient and what more could be done without switching from 4-layer to 6-layer PCB which I would like to avoid if at all possible. I see that ST's evaluation boards are made in 6 layers, I would like to believe that this is not a requirement for passing EMC tests.

Below is a picture of the point where I measure the massive ripple (RESET output):

[T3sl4co1l]

Layer 2 is solid?

That's still way more routing on layer 3 than I would approve.  And on layer 4, what traces are crossing those slots?  4 layers total, right?

Reset is generally a high impedance line, which implies some combination of three things:
1. The noise you measure is coupled in from a bypass cap, and the ground it returns to is dirty;
2. The noise is coupled from parallel traces, or crossing over particularly nasty ground slots;
3. The noise is common mode, and it appears when probing any net, including ground; the choice of RST was merely a coincidence, perhaps because it happens to be an inactive signal.

I recently routed a short SDRAM bus on a 2-layer board, which was probably a bit foolhardy, but it doesn't seem to be too noisy outside of the local area (as judged by a magnetic sniffer probe, and a bowtie antenna -- haven't done any conducted or radiated setups yet).  Key is the pinout from the host (an LCD controller), perfectly in order; the generous pitch (0.8mm) of the RAM chip doesn't hurt either, allowing me to route top and bottom traces with some ground pour around them.

Your situation is probably made less ideal by the MCU's higher pin density, longer routes, and possibly poorer pinout I'm not sure?  But that should be more than made up for by the ground planes.

Also, what all is on that big board-to-board header, besides RST?  And the LCD, is that driven by GPIOs or what?

Tim

[prasimix]

Layer 2 is solid?

Yes, more or less, please check all layers here.

That's still way more routing on layer 3 than I would approve.  And on layer 4, what traces are crossing those slots?  4 layers total, right?

Reset is generally a high impedance line, which implies some combination of three things:
1. The noise you measure is coupled in from a bypass cap, and the ground it returns to is dirty;
2. The noise is coupled from parallel traces, or crossing over particularly nasty ground slots;
3. The noise is common mode, and it appears when probing any net, including ground; the choice of RST was merely a coincidence, perhaps because it happens to be an inactive signal.

I made another measurement: move probe from RESET to GND (make short with probe GND cable). It doesn't look nice either:

Also, what all is on that big board-to-board header, besides RST?  And the LCD, is that driven by GPIOs or what?

Besides RST is backplane that carries up to three modules, but I made measurements with backplane removed, no improvement.

TFT is directly driven by MCU, I also tried to detach it completely and that also didn't help.

[T3sl4co1l]

Gah, just can't follow the traces.  Not enough visibility.

I'd have to look at the files, and preferably the physical build and what all was connected to it during the test.  And that'll take some hours to look at.

108MHz at least is on the low side, so if it's radiating, it's likely going up cables to do so.  We can already see something's going around (common mode) so that's very much possible, but I don't know how it was wired for testing.  The clock and harmonics are more likely to radiate from the board itself, though.

Is this important enough that you'd be interested in engaging professionally..?

Tim

[David Hess]

What kind of circuit is driving the reset signal?

There is a common reset circuit which involves an emitter follower which is prone to oscillation:

http://www.industrial-electronics.com/tac_9.html

[prasimix]

Gah, just can't follow the traces.  Not enough visibility.

I'd have to look at the files, and preferably the physical build and what all was connected to it during the test.  And that'll take some hours to look at.

108MHz at least is on the low side, so if it's radiating, it's likely going up cables to do so.  We can already see something's going around (common mode) so that's very much possible, but I don't know how it was wired for testing.  The clock and harmonics are more likely to radiate from the board itself, though.

Is this important enough that you'd be interested in engaging professionally..?

Tim

My first next step will be to redesign the PCB so that the SDRAM is as close to the MCU as possible (maybe I could put it on the bottom layer beneath the MCU!). If that doesn’t fix the situation I’ll start thinking about other options.

[prasimix]

What kind of circuit is driving the reset signal?

There is a common reset circuit which involves an emitter follower which is prone to oscillation:

http://www.industrial-electronics.com/tac_9.html

There is no reset circuit per se, only RC element. However the RESET line is all around the PCB and it is possible that due to its length and places it passes somewhere it picks up the clock frequency of the SDRAM.

[KE5FX]

Probing around on a board looking for EMI issues is usually a waste of time in my experience.  Nobody at the lab (or FCC) is going to be doing that.  If you don't already have a decent H-field probe, this would be a good time to buy or build one:



These can be used to good advantage with your scope as well as your spectrum analyzer. 

Another good video:

[prasimix]

I got Texbox EMC probe set with VNA, and already made some inspection, and will continue with that.

[jbb]

Hmm.
In the interest of not pulling your hair out, how about a quick bodge?
Connecting  C10 to nReset and Vcc is a little unorthodox; I would normally connect it to nReset and ground so that it pulls low at power up.
How about swinging C10 around to connect to ground instead?

Also, the STM32 might have a spread spectrum feature in the main PLL. Maybe that could spread out the energy over frequency and reduce the peak enough to squeak through?

[prasimix]

Yes, you're right, that capacitor doesn't belongs there. It remained as a "protection" from another phenomenon that I later found out what caused it (non-terminated debug cable that randomly knew how to reset the MCU). Anyway, if I removed it and probing the same place I got this:



Trying to move that capacitor from RESET to GND doesn't look good: it amplifies appearance of 108 MHz and its harmonics:

[T3sl4co1l]

It's just repeating the measurement we already know: there is a voltage drop from wherever RESET is anchored, to the pin.

Do you get a similar measurement from the bus lines?  (If there's no bus activity when the header is unplugged, just set them as active low.  If there is, override it to zero.)

Or active high. 

Purpose being, traces in a different environment (different neighbors) and supplied from a different IO bank, maybe there will be some insight about the MCU's power.

Also to clarify, you corrected the supply plane, but you're still testing the broken one..?

Also, in addition to moving traces off layer 3, I'd like to see via groups broken up: runs of vias cause large slots in both GND and VCC.  Nudging a few in the middle, just enough to get metal poured between, shrinks the opening by half.

Also also, I think I see a number of GND/VCC traces routed to the nearest via, which isn't always all that near?  Prioritize power pins and bypass caps, and if the connecting trace to any ground is more than say 100 mils, just drop a new via.  Vias are cheap.

Tim

[prasimix]

It's just repeating the measurement we already know: there is a voltage drop from wherever RESET is anchored, to the pin.

Do you get a similar measurement from the bus lines?  (If there's no bus activity when the header is unplugged, just set them as active low.  If there is, override it to zero.)

Or active high. 

Purpose being, traces in a different environment (different neighbors) and supplied from a different IO bank, maybe there will be some insight about the MCU's power.

In general, the situation looks similar on most of the pins of the 40-pin connector. SPI buses are live only if corresponding module is plugged in. The real difference makes disabling communication with SDRAM, possibly because it is not on the same potential as MCU (which has that isolated island od +Vdd connected with single point to the +3V3).

Also to clarify, you corrected the supply plane, but you're still testing the broken one..?

Yes, I still working with "broken" module, i.e. one that has isolated MCU Vdd power. Corrected L3 layout has to be manufactured if I decide to give it a try instead of complete redesign of SDRAM-MCU lanes with SDRAM on top or even moved to bottom layer.

Also, in addition to moving traces off layer 3, I'd like to see via groups broken up: runs of vias cause large slots in both GND and VCC.  Nudging a few in the middle, just enough to get metal poured between, shrinks the opening by half.

I'm not sure that I understand this one: what via groups?

Also also, I think I see a number of GND/VCC traces routed to the nearest via, which isn't always all that near?  Prioritize power pins and bypass caps, and if the connecting trace to any ground is more than say 100 mils, just drop a new via.  Vias are cheap.

When I started with layout, power pins were prioritized, i.e. decoupling 100n caps are placed near the MCU and SDRAM first. Caps GNDs are very close to pads.

[T3sl4co1l]

Stuff like highlighted --

Check layer 2, note the slots made by them.

BTW, the screenshots show tons of unconnected pads -- this is normal on the EDA side, and they're probably automatically removed in the Gerber output (or by the fab).  But it adds a lot of visual noise, especially when zoomed out, so it might be easy to miss, unless you're looking for it, or looking at the outputs.

Hmm, that's one thing Altium helps a bit with, pads and vias are drawn on the Multilayer layer, in gray (default colors).  Still a solid color, but less visual noise if you're looking for it.

Or if those are screenshots of the fab outputs -- enable "remove unconnected inner pads"!  It's a fab quality thing: extra copper puts more strain on the via plating.  Cheap fabs may remove it without asking (or leave it alone and not care..), full-service fabs will ask for confirmation.

Tim

[prasimix]

Ok, now I understand, but all that vias are functional, see how it looks when all 4 layers are visible:

[T3sl4co1l]

I didn't say delete, I said nudge.

[KE5FX]

Going to take a wild guess here and say that those particular vias are not a smoking gun.  I will say that I like to use more ground plane stitching vias than I'm seeing here.  I don't think I've ever generated a non-trivial board with less than two or three thousand vias total, most of which are plane stitching.

One concrete action item would be to provide via stitching around the periphery of the board.  Maybe one via per centimeter.  Otherwise, you have four large slot antennas.

What were you able to observe with the H-field probes?  Any leads there?

[T3sl4co1l]

Yeah, I'm guessing they aren't the problem either.  I listed that, among other things, as things that can be cleaned up.

I wonder if anything's resonating around 108MHz.  Could that plane under the MCU be doing it?  Or the plane around it, which is heavily cut up by the MCU plane and signal traces around it?

What if you swap out some bypass caps for lossy ones (R+C or tant)?

Also, can you highlight the VCC bypass caps and their connecting traces and vias?

Stitching is N/A on a 4 layer board without top and bottom pours, but I wonder if the next closest thing would be worth looking into: spread bypass caps around the board.  Remember, it doesn't much matter where caps are, with respect to pins; current is drawn from the plane, for the most part.  Local bypass is only meaningful when there isn't close access to the plane.  And use lots of vias (e.g. two vias per pad, flanking the body of the bypass cap) and short traces.

Rather hard to implement at this stage (on the physical board), but some evaluation can be made along that direction.  For example, find nearby GND/VCC pads in a given location, and attach coax very close to them.  Add ferrite beads to the coax.  Scope the supply ripple, AC coupling, 50 ohm terminated.  If a location doesn't have pads that are well enough isolated to test (i.e. don't use vias/pads on an active device), you can always dig down and expose planes directly -- it's destructive and a pain in the ass, but it can be done!  (Caps can be added in the same way, if you're really desperate.)

Tim

[jbb]

Tidying up the EMC design for the next release is well and good, but it’d be nice to tweak the existing board enough to pass.

Is there any opportunity to turn down the drive strength of the STM32 IO pins on the memory bus? That might squeeze out a few dB improvement.

How much are you over the emissions limit by?

Also, lab time can get expensive. Can you get some other ‘Debug’ testing done? Maybe ESD (could be an issue with user interface and SD card slot) and conducted interference (could be an issue with Ethernet port)? Would be very annoying to spin board for emissions issue then find ESD issues you could have fixed at same time.

Oh, yes, an applicable ESD story. The product I’m developing uses a flexible ferrite sheet for RF reasons. It’s allegedly an insulator.  But when you hit it with ESD, it conducts the ESD strike! I think it’s made of tiny ferrite lumps in a polymer carrier, and ESD jumps from lump to lump.

This resulted in ESD getting into an analog circuit some centimetres away from the strike, which was confusing.

[T3sl4co1l]

Heh, good point.  Ferrite itself has a modest dielectric constant (on top of being a mediocre conductor), makes sense.  Even if the composite material isn't a conductor (at least at normal voltages), it's still got a modest dielectric constant.  And yeah, probably broke down at high voltage.

Tim

[KE5FX]

Stitching is N/A on a 4 layer board without top and bottom pours

Good point there as well.  Boards without extensive top/bottom copper fill coverage scare me.  Arguably to an irrational extent, but still...  I don't like to remove copper without a good reason.  Why decline the offer of free shielding?

[floobydust]

I had the same issues as OP on a build using NXP processor with external SDRAM, 6-layer board. Basically, I found the CPU was spewing out a lot of EMI in the FM band, it even made out on the line cord as CM conducted emissions 

I tracked the FM carrier down to the SDRAM (auto) refresh clock. Those peak currents are very high, easily 200-400mA depending on the SDRAM size/speed and core voltage. On the bus, it's a few V/ns rise-times, so the transceivers are also switching hard.
So (my theory) the high current spikes on the CPU's address/databus seems to make its entire silicon "dirty", where other I/O something like RESET unexpectedly has a 100MHz signal present.

To fix it, I had the guy redo the PCB layout. Moved the SDRAM closer to the CPU, bus traces were not the proper impedance, beefed up the ground plane connections and upsized decoupling capacitors with pcb traces/vias support for higher current.
I added the usual series resistance on all CPU I/O pins that went anywhere significant, 47-220ohms is common on consumer electronics. As an RC filter rolls that off any high-frequency mischief coming out of a CPU. The C is either the next component, or added a few hundred pF after the resistor i.e. serial data at 115kbps was not bothered but no 100MHz drama making it out to the serial transceivers which could then pass it to external cables.
The product then passed EMC but it was a lot of work. Literally, every CPU pin I had to consider where it went and the consequences of high frequency EMI being present.

[prasimix]

I wonder if anything's resonating around 108MHz.  Could that plane under the MCU be doing it?  Or the plane around it, which is heavily cut up by the MCU plane and signal traces around it?

I'm not sure that is a problem, since when we slowed down SDRAM clock to 72 MHz the same things happen on that frequency. Ok, there is a still chance that some parts resonate at 108 and another on 72 MHz

[prasimix]

I had the same issues as OP on a build using NXP processor with external SDRAM, 6-layer board.

Thanks for this info, so i won't think jumping on a 6-layer will solve things on its own. I will have to concentrate on redesigning the existing 4-layer PCB and the result will become here. I believe that more pairs of eyes will find it easier to find potential sources of problems.

[prasimix]

How much are you over the emissions limit by?

Measurements with antenna oriented horizontally:



... and vertically: