EMI issue with bad power plane and SDRAM

[T3sl4co1l]

Pictures of testing setup?

It's not surprising that horizontal polarization is worst (assuming this was tested in a horizontal orientation as pictured), but it's interesting that vertical rejects most of that wideband noise except for the clock tone.  What would be radiating that?

I wonder if anything's resonating around 108MHz.  Could that plane under the MCU be doing it?  Or the plane around it, which is heavily cut up by the MCU plane and signal traces around it?

I'm not sure that is a problem, since when we slowed down SDRAM clock to 72 MHz the same things happen on that frequency. Ok, there is a still chance that some parts resonate at 108 and another on 72 MHz

By "around", I mean it might be damped enough to act as a wider bandpass.  Multiple resonances is another possibility, yup.

Tim

[prasimix]

I have just a few, here you can see antenna in vertical position, and used Keysight EMI receiver:

[T3sl4co1l]

Okay but those are 100 and 50 pixels respectively of the thing I actually wanted to see.

Tim

[prasimix]

Sorry, that's all what I have.

[KE5FX]

It would sure suck if it turns out you're actually measuring the laptop, which might have 'theoretically' passed testing at some lab in China which most assuredly was totally aboveboard. 

The last time I was in a test cell, there was a convenient platform for PCs and other ancillary gear on the floor beneath the turntable.

[prasimix]

I didn't notice anything "Made (cheap) in China" in that lab. Computer is brand name (DELL or Acer, cannot remember) and yes, to be completely sure we made measurement when it was only turned on and it is well below Class B as it should be.

[prasimix]

I started working on a new PCB. The first attempt was to bring SDRAM as close to the MCU as possible. However the pins on the MCU assigned to SDRAM do not appear to be optimized for such a setup. I continued to move SDRAM to the bottom layer. After several attempts to route with different orientations of SDRAM versus MCU I came up with a case that seems pretty good to me. I managed to route all traces to be 20 +/-0.5 mm with the exception of two: RAS and WE (CS). I only used top and bottom layer, 4-layer PCBs. So far, all decoupling capacitors and all traces between MCU and SDRAM have been positioned.
I'm not sure if I can use serpentine for address lines. I know they can be used for data lines and they should not be used for control and clock signals. I have not used more than one via per route.

Top and bottom layer detail:



Bottom layer only (with top silk mask for better visibility of MCU position):



SDRAM wire lengths:

[Dulus]

Precise length tuning at these frequencies/trace lengths are really not usefull at all.
±20% would easily suffice i would say.
I would go for the highest ground coverage possible.

Maybe you can place the chips as in the attached drawing. Seems to me that most of the traces seems to benefit from it.
MCU is red, RAM is blue =D

From previous posts, it seems that you've sorta kinda located the culprit traces.
You can try RC snubbers at the trace ends, near the chip pins.
Since the traces are not impedance controlled, and the input impedance of the chip pins are not really defined, traces can ring and emit a higher amount of EMI than it normally would.
So you can "terminate" these high frequency components on those high speed pins, therefore cut the emission or crosstalk or whatever you wanna call it.
Just get a scope and go trial&error on its ass...

Best of luck.
Deniz

[prasimix]

Thanks for the good wishes, I really need a lot of luck here. I tried to go with as short traces as possible assuming it could generate less EMI. However I think the real challenge is to achieve the desired impedance of 50 Ohms. Going from top (layer 1) to bottom (layer 4) I don't see how feasible this is. With a used width of 10 mils  and the assumption that the PCB manufacturer will respect the distance between the top and ground plane (Layer 2) of 7 mils, this gives about 54 Ohms (with a width of 12 mils we would have 50 Ohms). Moving to the lower layer completely disrupts this calculation and the impedance jumps over 100 Ohms if referenced against Layer 2 (or it could be referenced against Vdd on Layer 3, too?).

I don't see how SDRAM should be set up against the MCU so that all routes are only on the top layer. This would only be feasible if all assigned MCU pins for SDRAM were on one side instead of all four.

I didn't know it was possible to use RC snubbers in cases like this. I would love to see some examples, this would help me plan their deployment. RC components I guess should be very tiny 0603 or even 0402?

[BrianHG]

Thanks for the good wishes, I really need a lot of luck here. I tried to go with as short traces as possible assuming it could generate less EMI. However I think the real challenge is to achieve the desired impedance of 50 Ohms. Going from top (layer 1) to bottom (layer 4) I don't see how feasible this is. With a used width of 10 mils  and the assumption that the PCB manufacturer will respect the distance between the top and ground plane (Layer 2) of 7 mils, this gives about 54 Ohms (with a width of 12 mils we would have 50 Ohms). Moving to the lower layer completely disrupts this calculation and the impedance jumps over 100 Ohms if referenced against Layer 2 (or it could be referenced against Vdd on Layer 3, too?).

I don't see how SDRAM should be set up against the MCU so that all routes are only on the top layer. This would only be feasible if all assigned MCU pins for SDRAM were on one side instead of all four.

I didn't know it was possible to use RC snubbers in cases like this. I would love to see some examples, this would help me plan their deployment. RC components I guess should be very tiny 0603 or even 0402?

When using a single ram chip, in the past, I've tuned and used just series resistors alone to minimize EMI.
With such a low speed ram chip, length matching is a waste of time.  The fact that all signals go through only 1 single via in you layout will keep any big timing inconsistencies in check (IE, a few signals going through 3 vias instead of 1).  I have routed 200MHz DDR, 400mtps designs in this way without any issue.  Above 600mtps was when length matching began to become important.

1 big hint, all ram chip controls and clks should have their series resistor on the same side as the CPU and close to the CPU output pin as possible.  This way, you are not conducting a really harsh transition through a length of trace and via.

For the data IO, the series resistors should go next to the IC which has the faster output data.  You should be able to scope this and measure whether the CPU output is faster, or if the ram chip data output is faster.  (It is possible to use 2 series resistors, 1 by the CPU and 1 by the ram data IO pin to absolutely minimize harsh EMI.)

This will minimize EMI coming off your PCB other than additional layout and shielding efforts.

[T3sl4co1l]

The recent build I mentioned, oh I suppose I should drop in a (poor) picture of it;



the memory bus traces range from 408 to 1337 (nice) mils in length, also with the CLK going double back to a return pin (I guess so the controller can estimate propagation delay itself?).  Probably the return clock wasn't necessary at this bus length, and can be returned at the controller.

I don't have a scope quite fast enough to measure the full waveform, but from what I can see, the waveforms aren't noisy (supply is quiet), have modest overshoot (about 20%), and little ringing.  Likely a consequence of the high trace impedance combined with pin capacitances, and the pin drivers being typical CMOS strength (30-70 ohms).  (I measured CLK with a 10x lo-Z probe, which will have some damping effect compared to the ~100 ohm traces; again, 2-layer board.)

I don't see much conducted from the cables, and as you can see, the memory is off to the side, completely surrounded by stitched ground pour.  Supplies are well bypassed (there are three 0.1's on the RAM, and three nearby on the controller's VCC and VCORE pins on that side).  Ground is nearly solid, with exceptions made for traces crossing to the far row (including the CLK return signal), and VCC.  There should be very little way for noise to go anywhere, even though it is quite a noisy location as attested by the near field probe.

Layout:



Top and bottom, transparent




Top alone




Bottom alone


Notice VCC comes from the corner of the controller chip, and "uselessly" switches layers under the bus (which happens to be most of the DQs), allowing ground to fill underneath.

I'm sure I could've optimized the bottom side routing better, perhaps even pouring ground between every trace, not just pairs.  Breaking up the large group, the four parallel traces (half of which happen to be CLK!), would be nice.  But of course, how nice that is, depends on how much it really matters; clearly the circuit is functional, and beyond that, I don't have much more I can test.  (Perhaps the overshoot is triggering ESD diode conduction, perhaps it's causing increased current consumption, or stress, I don't know.  I'd need much fancier test equipment to figure that out.)

There is a bus running around the SDRAM, just out of view, but you can see corners to the bottom-left and bottom-right.  These of course would not be a great idea to route under it (but on a 4-layer design, that wouldn't matter).


Keep in mind that,
1. We still have not confirmed why and where the noise is being conducted on your board (incomplete testing information);
2. Multiple changes have been proposed, all of which are expected to have some effect on performance;
3. You have approximately zero intent of checking all of those proposals individually -- at least I'm guessing you aren't going to spend months, and tens of thousands of dollars, testing a prototype for each change.

It is quite possible that your initial change has already solved the problem to an adequate degree, and all the rest of this is just masturbation.  (Which makes this a good kind of thread for people like me to brag about our glossy routes and stitched planes, but not a very productive thread otherwise...)

Tim

[BrianHG]

These 2 sizes of 4 in 1 were optimum in my designs.
I would use the width matching the QFP/TSSOP pin spacing.
Obviously you might use a different values.

Chip Array Resistors example

Larger arrays of 8 resistors exist, but, I found 4 the optimum.

[prasimix]

Keep in mind that,
1. We still have not confirmed why and where the noise is being conducted on your board (incomplete testing information);
2. Multiple changes have been proposed, all of which are expected to have some effect on performance;
3. You have approximately zero intent of checking all of those proposals individually -- at least I'm guessing you aren't going to spend months, and tens of thousands of dollars, testing a prototype for each change.

It is quite possible that your initial change has already solved the problem to an adequate degree, and all the rest of this is just masturbation.  (Which makes this a good kind of thread for people like me to brag about our glossy routes and stitched planes, but not a very productive thread otherwise...)

It will be very good if you are right and that just fixing the MCU power supply fixes the problem, especially because I don’t have the time and money for multiple new iterations. Maybe I should proceed with two PCB variants: with corrected +Vdd on L3, and maybe another one with relocated SDRAM.
I tried with H-probe to sniff over MCU and SDRAM. MCU is significantly more noisy. This is what a typical spectrum looks like:



SDRAM seems more "defined" which I guess is to be expected:

[T3sl4co1l]

What's running, by the way?  In my case I have continuous SDRAM access because it's scanning a raster, and so also everything after that (the interface driver and display panel, but those are LVDS so the emissions are quite modest).  But I don't have any display updates written in yet so the MCU interface isn't doing anything (besides supplying clock to the controller's PLL), so I don't see anything on that cable.

Is that doing basically the same thing..?  Didn't look up your MCU, but it looks to be a similar sort of thing, raw parallel RGB to the panel, via controller peripheral?  With direct access (DMA or otherwise) to the SDRAM, I would suppose?  If so then that should be reading lots of data out, with corresponding sidebands visible around the SDRAM.  Or at least subharmonics for address lines (which are towards the end pictured, I think?).  It was initialized and running, right..?

Was that corner of the MCU the loudest, or anything?  (Or the SDRAM for that matter, too.)  How does it vary (intensity and spectrum) over the chip?  What else is running, what sorts of functions, or peripherals?

Any other spots on the PCB, top or bottom?  Might use a smaller probe to sniff up close to bypass caps for instance, or some traces, see if there's anything suspicious.  Not that bypass caps shouldn't be noisy, of course the ones close to the chips should be carrying a fair amount of signal currents; but it would be peculiar if signal currents are found at a distance, in unexpected places.

Tim

[prasimix]

What's running, by the way?  In my case I have continuous SDRAM access because it's scanning a raster, and so also everything after that (the interface driver and display panel, but those are LVDS so the emissions are quite modest).  But I don't have any display updates written in yet so the MCU interface isn't doing anything (besides supplying clock to the controller's PLL), so I don't see anything on that cable.

Is that doing basically the same thing..?  Didn't look up your MCU, but it looks to be a similar sort of thing, raw parallel RGB to the panel, via controller peripheral?  With direct access (DMA or otherwise) to the SDRAM, I would suppose?  If so then that should be reading lots of data out, with corresponding sidebands visible around the SDRAM.  Or at least subharmonics for address lines (which are towards the end pictured, I think?).  It was initialized and running, right..?

It's doing "nothing" ... SDRAM is used as frame buffer and this picture is displayed on the TFT screen:

[prasimix]

Was that corner of the MCU the loudest, or anything?  (Or the SDRAM for that matter, too.)  How does it vary (intensity and spectrum) over the chip?  What else is running, what sorts of functions, or peripherals?

Any other spots on the PCB, top or bottom?  Might use a smaller probe to sniff up close to bypass caps for instance, or some traces, see if there's anything suspicious.  Not that bypass caps shouldn't be noisy, of course the ones close to the chips should be carrying a fair amount of signal currents; but it would be peculiar if signal currents are found at a distance, in unexpected places.

This probably asked for more trained eyes and hand. The spectrum and intensity slightly vary over the different side of the MCU. On SDRAM side there is almost no fluctuations. If we go back to the beginning where I found that it is the communication with SDRAM that makes a lot of noise, it turns out that the main cause is really a bad MCU's power rail.

[prasimix]

Yesterday I completed two new MCU modules that have already been discussed. The first has only MCU +Vdd corrected, and the second has SDRAM placed beneath the MCU.

If measured at the same point as on the existing MCU module r2B4 the first correction does not seem to have helped: 108, 324 and 540 MHz are still very pronounced:





However, in the case of the second correction when the SDRAM was set beneath the MCU, there was a significant improvement:







Of course this still does not say whether we are within the radiated emission limit or not. We'll find out soon in the lab.

[prasimix]

Today we passed radiated emission with a corrected MCU module r3B3 that has SDRAM beneath the MCU. This is what the worst case with max. load looks like for the antenna placed horizontally:



This is what it looks like if the antenna is placed vertically:

[void_error]

I'm wondering if the EMI issues for the first board were caused by the return currents through the ground plane not following the signal traces (large loop antenna?). I'm no EMC expert (or any kind of expert for that matter) so take that as a question.  I'm asking this since I'm in the process of routing (or shooting myself in the foot) a similar STM32F7 board with two SDRAM chips and although it doesn't need to pass any EMC tests (small batch for personal use) I want to make sure It doesn't spew out tons of radiation. Don't want to hijack this topic so I'll probably start another one when I have it done.

[prasimix]

Hard to say anything. I'm not even close to be an EMC expert. Ground plane wasn't broken on the previous version, but Vdd for MCU was. I made another prototype with that correction, but it still behave much worse then prototype with SDRAM beneath MCU.

[void_error]

To be more specific, I was comparing the layout T3sl4co1l posted (where the traces from the controller to the RAM chip are pretty much straight) to your first board where the top layer traces from the RAM chip to the MCU look like the letter 'L'. I'm curious whether that makes a difference. With the really messy pinout of pretty much every STM32F series micro it's nearly impossible to get a clean layout.

[T3sl4co1l]

Nah, topologically speaking, an 'L' over a ground plane is practically a straight line.  It'll have some different emission (gain and pattern) at very high frequencies (i.e., where the leg of the 'L' becomes resonant), but at low frequencies (where it's electrically short) it really doesn't matter.

Willing to bet, in my case, the fact that the traces are so much higher above the plane, and that the plane is as cut-up as it is, dominates over trace length or shape.

Tim

[SiliconWizard]

Willing to bet, in my case, the fact that the traces are so much higher above the plane, and that the plane is as cut-up as it is, dominates over trace length or shape.

I agree, and would personally put all the power planes "slots" as the first source of problems. As it is they don't even really look like proper power planes anymore.