SG3525 oscillator asymmetry when error amp is maxed out.

[Circlotron]

Hi all.
I have an interleaved voltage-mode boost converter (mentioned on these pages before) that uses both sides of a SG3525 to drive two MOSFETs in anti-phase for use in an automotive environment. Inductors are off the shelf 220uH powdered iron toroids. Input voltage is nominally 12V and output can vary between 15-25V. Output is 20 amps and switching frequency is 22KHz.

When there is a high step up ratio the pulse width goes out to maximum (~45%) and the error opamp swings fully high. It is then out of regulation of course, but in this application it is not a big deal.

The problem is, when the error amp goes fully high the sawtooth PWM clock is not perfectly spaced every cycle. Every second cycle is about 10% shorter and this causes a great deal of current imbalance between the the two inductors. One will run hot and the other almost cold.

Has anyone else seen this problem?
I know there are better controller chips available but I'd really like to stick with the SG3525.

[Circlotron]

Further to the above, I disconnected the inductors to make sure there is no switched current floating around the board to upset things. In any case the board has a ground plane on the top and bottom layers.

The oscillator sawtooth swings from 0.6V up to 3.4V.
When the error amp output goes higher than 3.2V the sawtooth gets jittery.

[doktor pyta]

Try adding 10n...100n capacitors between pins 8,10 (and off course 12,15) to ground.

[Circlotron]

^^ Done that already.
I had some success by changing the value of the timing cap discharge resistor. Was using zero ohms with 1nF which should have been alright according to the datasheet, but now I have 390 ohms, and now there is only a tiny flicker as the opamp voltage goes through the critical range but once above this point it all comes good again. So, as far as I am concerned it is fixed.

I might yet change the oscillator parts from 1nf/33k to 10nF/3K3 to lower the impedance of that part of the circuit.

[bktemp]

SG3525 was often used for driving push-pull converters. Any asymmetry would saturate the transformer, therefore this problem is unusual.
ONsemi datasheet has a detailed schematic of at least the oscillator and some other input/output related parts. It shows a direct connection from the CT pin to the PWM comparator that could explain how the clock can be affected. It also shows the NOR gate structure generating the output signal. It looks like there is no direct connection between the flipflop and the CT pin, therefore it is odd that only every second cycle is affected. The only common signal is the reference voltage at pin16 beeing used as the supply voltage for most of the internal stages. Is this voltage stable?
Did you try another SG3525?

[T3sl4co1l]

What, you're using a single regulator to control two inductors?  This is insane, at best.

The inductors have independent currents, therefore they must be controlled by independent current error amps.

The only circuitry that can be common is the voltage error amp and the clock generator (which fortunately can help us out by providing a phase sequence, reducing ripple).  Well, and any common bias and reference and supply bits.

If you're in discontinuous mode, the currents will track by happy coincidence, only.  In continuous mode, both inductor currents are open variables!

Afraid I don't have any insight to the apparent pulse mismatch.

Tim

[David Hess]

SG3525 was often used for driving push-pull converters. Any asymmetry would saturate the transformer, therefore this problem is unusual.

I have also seen the SG3525 and the similar TL594 run open loop to make a two phase power transistor driver with dead time control for inverter output stages.

The relatively high output current combined with fast transitions may require more than a small ceramic decoupling capacitor if the bulk decoupling capacitor is located at a distance; I usually include a small solid tantalum or aluminum electrolytic capacitor for additional decoupling of the IC at least during development.

Also make sure there is no coupling between the fast digital outputs and the analog pins including through ground loops.