EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: JJalling on August 20, 2024, 06:07:03 am
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Hello,
I had a brief discussion with a co-worker about a design we are working on, where we use a voltage divider into an ADC, to "program" the board/HW revision for the firmware to detect.
The microcontroller we are using is a MSP430FR5969-SP.
Our circuit does look like this. No buffer or anything, just the voltage divider directly into the ADC.
[attach=2]
When comparing this to the circuit in the MSP430 user guide (https://www.ti.com/lit/ug/slau367p/slau367p.pdf (https://www.ti.com/lit/ug/slau367p/slau367p.pdf) , fig. 34-7, pg. 875) - what resistance is the ADC seing. Or in other words, what is the equivalent of Rs?
[attachimg=1]
I would say somewhere near the 32k (top resistor in the divider), whereas my co-worker is saying that it is 32k in parallel with the 1k. Who is closest to the answer?
BR Jonas
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Your co-worker is correct it is 1k in parallel with 32k bypassed by the cap, or just under 1k. It's the Thevenin equivalent.
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Thank you!
BR Jonas
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Yeah but you are having that Cpext with a large enough value to make a difference. Equivalent series resistance of the capacitor is near zero. And the capacitor supplies the ADC input.
The tad below 1k impedance of the resistor divider then supplies the capacitor. If you sample at high sample rates, capacitor has no time to charge from this divider network, and the 1k impedance of the divider dominates in ADC error. But if you sample rarely (maybe once, or at a few tens of Hz), then the capacitor's low ESR dominates and the 1k impedance of the divider is meaningless.
In other words, without capacitor, resistor divider impedance has to be low enough relative to sampling time. With capacitor, resistor divider impedance has to be low enough relative to sampling period. These are usually very different; sampling time might be configurable on the ADC, but it could still be microseconds. Period is as chosen by ADC trigger logic; e.g. you can trigger it in software or using a timer only at, say, 1Hz.
You can expect error in the ratio of that capacitor and internal sampling capacitor. 10nF is kinda awkward value because while it is large enough to work, it is small enough to limit accuracy around 10 bits or so (with typical C_sampl values of around 10pF). You likely have a 100nF or even 1uF part in your BOM already, so use it instead and get a few extra bits, of course limiting bandwidth even more, but that is already limited anyway due to unbuffered resistor divider.
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The tad below 1k impedance of the resistor divider then supplies the capacitor. If you sample at high sample rates, capacitor has no time to charge from this divider network, and the 1k impedance of the divider dominates in ADC error. But if you sample rarely (maybe once, or at a few tens of Hz), then the capacitor's low ESR dominates and the 1k impedance of the divider is meaningless.
With the caveat that a capacitor cannot correct for ADC input leakage current. Modern ADCs tend to have low leakage, but that's not always the case e.g. some of the 18F PICs were pretty poor.