PSRAM Layout Considerations

[Evan.Cornell]

I am working on a design with STM32H743 and IS66WVE2M16EALL-70BLI (32Mbit PSRAM). Since the PSRAM part has a max page access time of 70ns, I assume that means the fastest I could read guaranteed data out would be 1/70ns = 14.2MHz.

In terms of the hardware design, this isn't very fast at all, so am I correct in thinking that I don't need to be particularly careful about either length matching or impedance controlling all the signals between the STM32 and the PSRAM part?

[David Hess]

In terms of the hardware design, this isn't very fast at all, so am I correct in thinking that I don't need to be particularly careful about either length matching or impedance controlling all the signals between the STM32 and the PSRAM part?

That is correct, with the caveat that fast edge speeds still need to be accounted for.  70 nanosecond access times were handled by TTL technology decades ago which gives some idea of the required design rules.

Access times for DRAM have not scaled up nearly as much as clock speeds over the decades so design rules are much more stringent now for what is essentially the same access time.