ESP32 minimal board with ethernet (LAN8720)

[nuclearcat]

Just finished testing minimal board (that i will use as ESP-NOW to Ethernet gateway and base for future projects) and published under opensource license.
Minimal Arduino project included, should be compatible with SDK examples as well.
Contains all info(gerbers, pos, bom) required to order on JLCPCB.
Comments are welcome.
https://github.com/nuclearcat/ESP32ETH

[nuclearcat]

Thanks for the OSHW/SW!

How do you find the efficiency / performance / throughput is using the ESP32 ethernet controller / MAC with the external PHY you have selected?

Do you recall what other interfaces of the ESP32 are subsequently impossible to use because of pin contention when using the RMII interface and talking to the PHY presumably by some kind of GPIO / MDIO etc.?

I didnt stress-tested much, except just various icmp test-patterns (usually it is enough to find issues on low level stack), including flood ping. Pulled about 30GB both direction without any error, which means i am withing specs for BER.

Can't recall exactly, but on other project i had issues with way less pleasant routing for other PHY, maybe IP101?.  This board likely wont pass EMI tests as it is 2 layer and because of that routing is more painful if board is more populated than this minimal design. But anyway, it is still 100Mbit, so it is very forgiving

Main trick with ESP32 is how PHY can be clocked, as there is several configurations possible.
1)We clock PHY by crystal, then we feed ESP32 to GPIO0 which i consider not really great by multiple reasons (BOM, GPIO0 need to be routed for programming pin so impedance will suffer, etc etc)
2)Use GPIO16, i was getting out of phase issues sometimes.
3)GPIO17 as i did, phase issues seems corrected by inverted clock, downside that this pin might be used by PSRAM in some modules.

[globoy]

Thanks for sharing your design!  Nice to be able to use GPIO17 as PHY clock out without having to invert it externally.  Bummer it isn't available for modules with PSRAM.

I have a couple of quick questions.

1. There doesn't appear to be a capacitor to ground (e.g. 1 uF) on EN.  Is there any risk that the ESP32 will enter serial boot more on power-up since EN and GPIO0 are going high at the same time?

2. In general how are you finding availability of PHY chips?  I'm creating a design and when I started LAN8720A parts were unavailable but I did find availability of IP101 (designed into my current layout).

[nuclearcat]

Thanks for sharing your design!  Nice to be able to use GPIO17 as PHY clock out without having to invert it externally.  Bummer it isn't available for modules with PSRAM.

I have a couple of quick questions.

1. There doesn't appear to be a capacitor to ground (e.g. 1 uF) on EN.  Is there any risk that the ESP32 will enter serial boot more on power-up since EN and GPIO0 are going high at the same time?

2. In general how are you finding availability of PHY chips?  I'm creating a design and when I started LAN8720A parts were unavailable but I did find availability of IP101 (designed into my current layout).

1. Never seen that yet, i have quite many boards done such way. I wonder if anyone else faced such issue? Maybe it is good to make "ESP32 minimal circuit checklist" then, with such notes.
2. I can say "never disappeared for long time", but you know, it's all unpredictable these days.

[danilo_prof]

Hi, could you please explain how to import your project in Easyeda?
tks