| Electronics > Projects, Designs, and Technical Stuff |
| Ethernet link detection |
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| rakeshm55:
Hi, Assuming 1. A generic 10/100 Ethernet PHY 2. Using the general purpose registers What is the logic used by controllers to detect link from an Ethernet PHY. Do they keep on polling the link up bit from the register set?? If so How frequent do they poll this register via MDIO?? Is there any literature or code snippet (C code ) for this ?? My purpose is to use FPGA (vhdl) to detect link up/down from an Ethernet PHY. As I understand there are PHY dependent features like interrupt, but I would like to stick with general purpose registers. Once the approach is clear i can hand code vhdl for this purpose. So that FPGA an frequently keep track of link up and down status. |
| GeorgeOfTheJungle:
--- Quote from: rakeshm55 on November 12, 2019, 08:49:27 am ---Do they keep on polling the link up bit from the register set?? --- End quote --- Yes. --- Quote ---If so How frequent do they poll this register via MDIO?? --- End quote --- Every 1..5 seconds. --- Quote ---Is there any literature or code snippet (C code ) for this ?? --- End quote --- The PHY register set is a standard (IEEE 802.3). You just have to check bit #2 ("Link Status") of the basic status register (that's register #1). |
| rakeshm55:
On more query If there is continuous Rx activity (receive data) then will it hold the polling loop?? or reset the timer ??or they just keep on polling no matter what activity in Data receive. |
| GeorgeOfTheJungle:
I think the driver keeps polling no matter what. When it sees lost link, triggers a renegotiation. |
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