Hi,
Assuming
1. A generic 10/100 Ethernet PHY
2. Using the general purpose registers
What is the logic used by controllers to detect link from an Ethernet PHY. Do they keep on polling the link up bit from the register set??
If so How frequent do they poll this register via MDIO??
Is there any literature or code snippet (C code ) for this ??
My purpose is to use FPGA (vhdl) to detect link up/down from an Ethernet PHY.
As I understand there are PHY dependent features like interrupt, but I would like to stick with general purpose registers. Once the approach is clear i can hand code vhdl for this purpose. So that FPGA an frequently keep track of link up and down status.