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Evaluation of a 40V/5A DIY lab power supply

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TheJC:
Hi everybody,
I'm currently trying to build a lab bench power supply for myself.
It should reach 40V at 5A. I will also try to control it digitally with a µC.
So far I only designed the analog-power output stage of the supply I wanted to later add a Buck pre-regulator before the linear regulator.
I just want to know if this design is viable or should I just scrap the idea and begin new.


Thank you in advance for all your suggestions.

mikerj:
The INA169 has a minimum common range of 2.7v, so current sensing won't work at low output voltages.  Better to sense on the unregulated side of the pass transistor.

To get 40V out, the gate of the NMOS will need to be driven at 40v + Vgs at whatever current you are drawing (5 volts or so).  The LT1013's maximum supply voltage is 30v so that isn't going to work.

T1 introduces a lot of extra loop gain into the current regulator, so stability issues are likely.  Additionally you are loading the U1B output with a capacitor to ground, something else likely to cause stability problems unless an op-amp is rated for this (and I suspect the LT1013 isn't).

The 22uF cap on the gate looks pretty hefty, at best this is going to hurt transient response.

TheJC:

--- Quote ---To get 40V out, the gate of the NMOS will need to be driven at 40v + Vgs at whatever current you are drawing (5 volts or so).  The LT1013's maximum supply voltage is 30v so that isn't going to work.
--- End quote ---
The datasheet says it's okay up to a supply of 44V. But is only specified up to 30V. Anyway, I thought I try this opamp because I couldn't find a good alternative that is in stock and not as expensive. I originally had an eye on the ADA4522 that is better suited, as it is fully specified up to 55V.


--- Quote ---T1 introduces a lot of extra loop gain into the current regulator, so stability issues are likely.
--- End quote ---
Do you believe it would be better if I would replace T1 with a diode? To only pull the gate voltage down when current maxes out.


--- Quote ---The 22uF cap on the gate looks pretty hefty, at best this is going to hurt transient response.
--- End quote ---
Ok, might be too big. I will shrink it, it will oscillate with no cap there  :-\ 

David Hess:

--- Quote from: TheJC on August 20, 2019, 09:00:03 pm ---I'm currently trying to build a lab bench power supply for myself.   It should reach 40V at 5A.  I will also try to control it digitally with a µC.
--- End quote ---

I suggest starting at a lower voltage and current to get a better idea of what works and what does not work.


--- Quote ---So far I only designed the analog-power output stage of the supply I wanted to later add a Buck pre-regulator before the linear regulator.  I just want to know if this design is viable or should I just scrap the idea and begin new.
--- End quote ---

The design is not viable.  Scrap the idea and begin new.

1. T1 adds uncontrolled voltage gain within the current control loop which will make frequency compensation near to impossible.  Replace T1 with a diode and PNP emitter follower or use a different way to combine the voltage and current loops.

2. Cascading current sense amplifier U2 with current error amplifier U1B makes frequency compensation more difficult and is not necessary in any case.  Both functions can be performed in the same stage.  (1)

3. Output capacitor C3 is unusually small for a general purpose 5 amp supply but not for a higher performance one with faster current limiting.  But a low output capacitance per amp requires careful attention to frequency compensation.  Placing the current shunt in series with the output as shown actually makes this easier if AC feedback is taken from before the current shunt because it adds a zero (phase lead) to the frequency compensation just like the ESR of the output capacitor does.

4. C1 is useless and will just cause tears.

5. The LT1013 (and most operational amplifiers) will have difficulty driving the input capacitance of a power MOSFET output stage.  Consider adding a power buffer to improve performance.

6. C2 and C4 are attempts to meet outrageous frequency compensation requirements and should not be required.

(1) Instead of using current sense amplifier U2 to create a ground referenced voltage representing the output current, do it in reverse and create an output referenced voltage representing the maximum current.  In other words, level shift the current control signal to the output voltage level.  Then the error amplifier for the current control loop just follows the output voltage and there is only one stage.  (2)

(2) Of course this does not allow easy read-back of the output current level in a digitally controlled design.  I might use a separate current shunt amplifier as shown to make a ground referenced signal just for that although this makes calibration more complex.

Kleinstein:
The design Idea is no viable for several reasons. A point not yet mentioned: Using a high side shunt and instrumentation amplifier is very tricky, as the common voltage can be quite high compared to the small drop at the shunt. This is easy to cause problems at the high frequency end when the CMRR of even the good amplifiers get worse.

A MOSFET as a source follower is tricky, as the trans-conductance goes up with current - so in case of a short the current can spike to very high values. As a follower a BJT is more forgiving, as current gain tends to saturate at very high currents, kind of limiting with worst case current.

The concept with a transistor as a follower is easy for low voltage, but no longer simple at more than some 30 V, as the error amplifier has to drive such a high voltage.

For the beginning I would start with a much lower power (e.g. 0.5 A) version, to limit the amount of smoke to escape.

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