Electronics > Projects, Designs, and Technical Stuff
Experimenting with TTL Cpu, 74LS chips, old vs New? Retro style switches?
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tggzzz:

--- Quote from: rwgast_lowlevellogicdesin on June 04, 2020, 10:28:19 pm ---Just a curious question, when using the FAST or the A families cant you still reap there speed benefits whiles using appropriately sized resistors to slow the rising edge slow enough in order to avoid issues? People do this to control the rise time of a FETs gate all the time, and aren't the newer chip family's based on FETs is that part of what makes there layout issues so much more crucial? Seems like if you were going to use them without trying to slow there edges the key is low impeadence ground, and smashing there SMT versions as close together as possible to avoid trace length.

--- End quote ---

There are tradeoffs between propagation delay, transition time, fanout, wire length, and noise margins. If you are prepared to slug the output, it would be better to simply use a slower logic family.
T3sl4co1l:
Just generally all under the umbrella of signal quality.

Consider the chip's design itself, it's made of pins and bondwires.  Use the shortest pins you can get (prefer TSSOP over SOIC over DIP).

Try to avoid transitioning multiple pins high or low simultaneously.  This is particularly hard to avoid on, say, bus latches; at least they usually have schmitt trigger inputs, alleviating some concern with signal bounce and risetime.

Consider the entire net route, its drivers, receivers (input pins), ground support (keep it near ground plane as much as possible), and height above ground and trace width (which define the transmission line impedance).  Avoid tree routing; prefer linear (point-to-point-to-point) routing.

If the signal's minimum pulse width is much longer than the electrical length of the net, and there are no significant DC loads on the trace (which for TTL, means having a low fanout; for CMOS, it's pretty much whatever), source termination can be considered.  Note that the waveform at any intermediate node has a stairstep shape, as the incident and reflected waves cross it twice (which takes up to twice the electrical length of the net, hence the requirement that the pulse widths be much longer than this duration!).

Note that input pins have capacitance, so act to load down the trace.  If you have multiple inputs on a net, try to space them evenly so that they act more like a lumped-equivalent transmission line.  The trace impedance can be a little higher in this case, since the average including pin capacitance will be lower (impedance is sqrt(L/C), and the pins act to increase C).  There may still be ringing due to the between-inputs lengths, which can be dampened with additional resistance (say on a few of the inputs, or a small R+C at the end, or a FB at the driver(s)).

Speaking of ferrite beads (FBs), be careful using these; they have, not so much a long time constant, as, effectively, a distributed time constant.  In series, this will give nice, soft, rounded edges, which is good for reducing EMI on cables, but can be ill advised for high speed signals.  FBs are available in many values, so pick an impedance appropriate to the application -- for just taking off some ringing perhaps, a low value (say 10-30 ohms @ 100MHz) might be good, while for slower signals (especially going onto cables), larger values are an excellent choice (say 100 or 300 or 1k ohms).

And for cables, you might even add some parallel capacitance (or R+C) to provide additional filtering and dampening.  And maybe some ESD clamp diodes, because the outside world is a nasty place.

As for nets that can't so easily be source-terminated, load or source-load termination is an option.  This is quite traditional among TTL -- the relatively high driver voltage (roughly 0.4 to 3V typ.) and smaller input threshold range (0.8-2V) means some loss can be tolerated along the signal path.  A source-load terminated medium has, as the name suggests, a matched driver impedance (Zo at the ends, or Zo/2 in the middle), and termination at the ends (Zo for each end that doesn't have a permanent driver also attached*).

*Because Thevenin and superposition theorems.  A source at 0V (AC) and a series resistance of Zo, is... literally the definition of a termination resistor.  (More specifically, with 0V correlated to the driving source in question.  If they happen to be synchronized, they're not uncorrelated, and the effective impedance will be something else.)

Back in the day, divider resistor packs were quite common, something like 390 ohms pullup, 150 ohms pulldown -- the parallel combination being a perfect match to ribbon cable, when wired with alternating signal and ground, and the Thevenin equivalent voltage being perfect for TTL inputs.  The old ST-506 hard drive interface used exactly this for the control signals; the terminator was socketed, so it could be inserted in the last drive along the chain.  (The data signals however were preserved with better signal rate and quality, using RS-422 differential transceivers and point-to-point links -- hence one multi-position control cable and two separate data cables between the controller and a pair of drives!)

If you put a (IEEE 1284) parallel port on your project, you can consider using just such a termination with it; the transmitters are either 5V TTL, or 3.3V LVCMOS (typically 74HC family), either way having fairly comparable drive capability, suitable for load termination like this.

Which also tells you exactly how to construct it -- the old school way is literally an I/O address decoder, a couple bus latches, a bus interface (if full bidirectional), and, usually a 7406 or something (open collector) for the control signals I think?  (In PCs, this was quickly integrated into the system (SuperIO) chip, then later on, eliminated entirely.)


Ahem, anyway, signal quality doesn't need to affect your design much, or at all; it's not something you need much schematic consideration of.  For the most part, it is a separate and independent step, part of layout and routing.

If breadboarding, don't ignore it too hard -- your jumper wires are traces all the same, albeit with rather awful impedances, and relatively high coupling between them, making things more vulnerable.  Make sure the supplies are well bypassed and stitched (if using physical supply rails, tie them together at both ends of the board, say).  Maybe slip on a ferrite bead every so often, make sure the signals don't bounce too much.

Best part is, all this can be viewed on a typical scope (100MHz maybe isn't quite enough, but 200MHz or more is good), so you can see where signal bounce, supply noise, and common mode noise, are present.  You can always add or remove jumpers, and slip on ferrite beads as needed.  (Adding termination resistors would be harder to do!)

I once breadboarded a 4MHz Z80-CPU, with RAM, ROM, and a couple (74LS) bus latches, one pair of which drove an LED matrix display; it would often run fine, for days or weeks on end, but once I coded a LFSR (a type of random number generator), it would hang much more frequently (within days to hours).  Presumably, some bad combinations of data were causing the buses or supply to glitch; maybe improved bypassing, or grounding, or ferrite beads on some signals (or all of them?..), would've fixed it.  It goes to show you, something might look perfectly okay with average data -- the LED matrix routines were very repetitive -- yet an underlying problem hides in plain sight (in this case discovered by fuzzing with random bus data).

On another occasion, I had made an SPI peripheral module on a separate board, and plugged it into a breadboard with an ATMEGA; it was a disaster, just gibberish going through.  Slipped a ferrite bead on to SCK, MISO and MOSI, good as can be.  ATMEGA has faster pin transition times than some of what we're talking about here; with 74HC I think being, either a little bit slower, or comparable to it?

Tim
David Hess:

--- Quote from: tggzzz on June 04, 2020, 10:01:28 pm ---That tallies with my recollection, but one of the claimed advantages of FAST was that controlled edge rates minimised the problem.
--- End quote ---

That helped and what I referred to about the difference between bipolar and CMOS but they still never met their intended specifications.  SO packaged parts did better.  Non-saturating logic like ECL was much more forgiving.


--- Quote ---Putting the power pins on the opposite corners always was a pessimal choice.
--- End quote ---

Easier layout was a good reason to place the power and ground pins on the corners.  Later logic families moved the power and ground pins to the center of the package where appropriate.


--- Quote from: rwgast_lowlevellogicdesin on June 04, 2020, 10:28:19 pm ---Just a curious question, when using the FAST or the A families cant you still reap there speed benefits whiles using appropriately sized resistors to slow the rising edge slow enough in order to avoid issues?
--- End quote ---

Using a series resistor to slow down the edge and reduce ground bounce helps but does not restore any performance which was lost.  I only saw it done to control EMI as a last resort when a better design was not practical.
rwgast_lowlevellogicdesin:
Wow, thank you for that huge wealth of information, it's not every day you get I reply like that I will have to re-read it!

As far as front panel controls go, I'm no where near ready to implement them yet (pcb mount dip switches and jumpers are fine atm) but I've been looking all over and looking at old minicomputer and retro kit designs. Toggle switches like the ones on the PDP/IMASI/etc look like a huge PITA, from what I can tell you flip them in to the binary position you want and then hit a momentary store/continue button. So after that you have to manually flip them all back to 0? Using the front panel is already tedious but having to re 0 is just painful!! So using momentary rockers with latched LEDs seems a lot more productive, so the store/content button can be used to de latch the data switches and 0 them. I believe this is how the HP1000 refered to earlier did things? I'm sure in the day using momentarys in the way I described added extra cost/size do to the latching circuitry and the need for better debounce. I have no qualms about using a micro or plc to deal with the user interface though, I wouldn't learn anything new from doing it, and it just costs more and requires more room in the enclose that can be better utilized.

Now what I think would be a way cooler interface, that's totally unique is using STOP ACTION MAGNET rockers or something like them, for those who don't know there basically a SPST rocker which can be flipped by hand or electrically (both un and down) using solenoids, which in turn open or close a magnetic reed (although that part is not important). Here is a most likely very expensive example Sydney SAM which I'm sure exhibits awfully bounce. Something with electro-mechanical control like this could be made pretty easy though. Either by creating special rocker caps that a solenoid can push, or by using hall effect sensors if you want a cleaner signal with no bounce. If you had a setup like this you could make the switches automatically match the position of the stored data (when single stepping or running at extremely low clocks), as well as 0 out after store/continue. Unlike just latching leds to a momentary you get cool visual feedback and audio clacking. My biggest problem is designing the switch poles/caps I dont know anything about 3d printing or laser cutting nor do i live near a maker space so i would have to use my non cnc metal working skills to grind and braze them togather probably with aluminum, seems like a ton of effort and time but damn itd be cool!

Ps typed on my phone sorry about any misspelling or non sense auto correction I missed
T3sl4co1l:
How about a lever spanning all the switches that flips them to all 1/0 when you push on it. ;D

Oh or hey, speaking of latches, you could use pushbuttons to set or toggle flip-flops, and a couple buttons off to the side to set all 1/0.  Can have it reset automatically when entered, or persist.

Could also have a live decoder on the value being composed, say for hex (just run it into a hexadecimal display driver), maybe ASCII (same but one of those smart matrix displays, or anything fancier and custom), maybe a debug display as well (if your instruction set shall be fixed width, the mnemonic could be decoded in the same way, but with a lookup table, which could be a few ROMs storing text).

Which... for a variable length instruction set, you'd have to, I think, have two address counters, one showing the base of the instruction, and the other what's currently being entered (which can be just a few bits long, at least).  The decoder would test all bytes inbetween and decode the instruction accordingly.  Can certainly be done in hardware, but it's kind of at the point where you might as well put all the buttons into IO space and write a little bootstrap/debugger to handle the work instead...

Tim
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