### Author Topic: Explaining Gate Capacitance vs Gate Charge?  (Read 320 times)

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#### Hiemal

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##### Explaining Gate Capacitance vs Gate Charge?
« on: September 18, 2020, 04:52:56 am »
I've been spending a lot of time researching the difference between various power MOSFETs, and I'm a tad bit confused.

There's gate capacitance, and gate charge. I understand that as you increase gate drive voltage, gate charge increases. But, what is gate charge? What is it "measuring"?

How does this affect gate driving? I know gate capacitance seems to be the biggest thing most people look for in a mosfet, but yet, gate charge can seemingly vary WIDELY between FET's even of similar current and voltage ratings... whereas gate capacitance does vary, but not by quite so much a margin...

Example, these two mosfets:
https://static6.arrow.com/aropdfconversion/9ab7278098a3207dd829df705b92fd39089c2216/421505481485470966741-apt20m18b2-lvr-a-pdf.pdf

https://static6.arrow.com/aropdfconversion/d9e1a3a8c6b7acba600f0b773992325eed3f681c/infineon-irf200p222-ds-v01_02-en.pdf

The IRF200P222 has a gate capacitance of 9820 pF, and a total gate charge of 135 nC at 10 VGS. Rated at 200V, 182A.

Meanwhile, the APT20M18 has a gate capacitance of 9880 pF, but a total gate charge of 330 nC at 10 VGS! Yet, it's rated at 200V, 100A!

How does this work?

And on a different, yet related, note, why do people still use the standard IRFP4xx - IRFP2xx FET's so much, if there's much better FET's seemingly available nowadays? Is it because they're easy to drive? Or just more or less "tradition" in some sense?

#### magic

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##### Re: Explaining Gate Capacitance vs Gate Charge?
« Reply #1 on: September 18, 2020, 05:50:29 am »
Charge is charge - basically how many electrons (coulombs in SI units) need to be pushed/pulled in/out the gate to do something.

It varies a lot because test conditions vary a lot. For example, it depends on off-state drain voltage because of the Miller effect (gate-drain capacitance getting charged up/down).

The reason they give a second spec for "total gate charge" is because estimating it from capacitance is difficult. Capacitance varies a lot with drain voltage, see "typical characteristics".

#### T3sl4co1l

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##### Re: Explaining Gate Capacitance vs Gate Charge?
« Reply #2 on: September 18, 2020, 06:16:13 am »
Charge is the integral of current; or conversely, current is the derivative (rate of change) of current.

For switching purposes, you aren't so much concerned with when, and how much, current flows, just so long as it's done in the desired time frame.  For this purpose, you can use the equivalent capacitance, i.e., assuming the gate were a capacitor that stores the same amount of charge over the same voltage range.  Ceq = Qg(tot) / (Vgs(on) - Vgs(off)).

Then you need a gate driver either with resistance low enough, or peak current high enough, to achieve the desired switching time (assume gate rise/fall time is about t = 2.2 R Ceq, or t = Qg(tot) / Ipk).  Note that R includes internal gate resistance (R_G, sometimes given in the datasheet), driver resistance, and anything you add externally.  And likewise, Ipk isn't going to be any more than Vgs(on) / R_G, no point in using a 12A gate driver on a 5 ohm gate for example.

Load (drain voltage) switching time will be some fraction of gate switching time, usually around half.  Most of the drain voltage swing occurs during the Miller plateau, which consumes about half the gate charge, so there you go.  Give or take real numbers for a given device, and give or take load current (e.g. if an opposing transistor turns on hard, it'll yank the drain voltage up, ready or not..!).

Between your two examples, note that the APT- part gives switching times at R_G = 0.6Ω, which is the total (external + driver) resistance; they do not rate internal gate resistance.  (Presumably it's on the same order; otherwise, why bother using such a low driver resistance?*)  The IRF- part does give R_G, which is nice.

*This might not be a great question to ask: a lot of Fairchild (now ON Semi) datasheets use(d?) 25Ω for switching times.  Even when it was extremely unflattering, like 300ns here and there just because it's a beefy gate, when it can actually switch quite a lot faster, if simply driven harder.  When internal R_G is given, this is the more reliable spec I think; switching times are more just for reference.

As for capacitance -- I haven't mentioned that yet, and that's because it's a small signal parameter, measured in cutoff.  It's not very useful for switching purposes.  (Notice Vgs = 0, Vds = 25/50.)  The reason the APT- has so much more charge, is because the charge is dominated by D-G capacitance (Crss), which also drops off much more gradually (see Fig.11, compare IRF- Fig.7).  This is an older technology -- despite the 2015 date, it seems to be older VDMOS technology (or something like that).  The IRF part achieves a fraction of the on-resistance, even with a fraction of the die area**, thanks to newer SuperJunction technology.  You can tell this from the dramatic drop in capacitance as Vds goes up.

**More or less: power dissipation, avalanche energy and gate charge are proportional to die area.  The gate and source metallization spread over basically the entire face of the die, so that's a strong indicator.  Power dissipation also depends on how it's bonded and heatsinked, and 625W is pretty optimistic for that package (regardless of what die is in it).  Avalanche energy also trades off with body diode recovery, of all things, so it's not for sure.  In fact, if the IRF die is about 1/3 the area, it's still doing about the same avalanche energy density, but still has better body diode recovery -- another sign of just how much further refined it is.

SuperJunction also solved the issue of Rds(on) vs. Vds, which went quadratically in the past (i.e., for Vds doubled, Rds(on) quadruples, given the same die area).  It's proportional, or nearly so.  Obviously you can't tell anything about this from single datasheets, but if you look at parts in both families, looking at different Vds(max) while adjusting Rds(on) proportional to Qg, this should ring true.

Many SJ parts also have wide SOA (including down to DC).  Though this one definitely does not have it.  (The APT- doesn't even show DC SOA, though it doesn't show any dropoff in the 10ms curve.  The IRF- shows a rather aggressive cut, i.e. required derating at high Vds.  This is irrelevant for switching purposes, though, and you wouldn't want to use transistors this big in a linear circuit.)

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
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#### blueskull

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##### Re: Explaining Gate Capacitance vs Gate Charge?
« Reply #3 on: September 18, 2020, 06:22:55 am »
1. Current rating means nothing. It is calculated to be the current that drives the device to its maximum junction temperature at a given condition, such as a fixed ambient temperature or a fixed case temperature. Since the condition differs, the numbers have zero meaning. A better criterion is on state resistance.

2. Charge has little to do with capacitance. A MOSFET, during turn-on, goes through four phases (symmetric during turn-off), high-Z to start conducting current, current ramp up to full current, voltage fall down to near zero, and voltage fall down to minimum. In the first phase gate is charged from 0V to threshold voltage, in the second phase the gate is charged further to plateau voltage, then drain voltage starts to fall, and gate voltage remains, and in the last phase gate voltage is charged to designed full gate voltage, and conduction resistance drops to design target. In the third phase, as drain voltage collapses, parasitic capacitance between drain and gate pulls charge from gate, thus necessitating more charge than simply Cgs*Vgs. For high voltage devices, Qgd can easily be more than all Qgs combined.

3. People use old devices due to the outdated processes are less efficient, thus more silicon area is needed to achieve the same resistance at the same voltage, thus it can dissipate more heat. If you are after the most efficient and fastest design, you want the latest technology. If you are after robust and linear operation, you want the older larger die size design.

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#### dietert1

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##### Re: Explaining Gate Capacitance vs Gate Charge?
« Reply #4 on: September 18, 2020, 06:38:53 am »
The keyword is "Miller integrator". If you understand that you can predict rise and fall times depending on gate drive and device capacitance. You will find that gate charge also depends on output voltage swing.

Regards, Dieter

#### Hiemal

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##### Re: Explaining Gate Capacitance vs Gate Charge?
« Reply #5 on: September 19, 2020, 01:43:52 am »
So... to summarize what was said by everyone, if I'm understanding it correctly;

Gate Charge via the datasheet varies because of varying testing conditions, due to different internal and external gate resistors; you have to read a bit more into the datasheet to understand the exact differences between similar FET's, even if the numbers vary a lot.

Gate charge is specifically, how much "charge" is being pushed into a gate, in order to turn the mosfet on fully and keep it on throughout that switching cycle. Using oversized/overrated gate drivers doesn't help increase switching speeds if your internal gate resistance is too high vs VGS.

Gate capacitance is a somewhat "useless" measurement when trying to characterize mosfets?

So... okay. Continuing on then, how do you decide what mosfet to use when it comes to different applications? Obviously price is one such thing, but all else being equal would you typically go with a FET that has a smaller gate charge vs another if all else is the same? Is there a general sort of "rule" when it comes to deciding what mosfet is going to be better? I had always been going off of gate capacitance, since I hadn't ever been taught that anything else was important when it came to figuring out how "hard" it was to drive a certain mosfet. I always figured it was just, capacitance that had to be discharged and recharged and the bigger the capacitance, the more "oomph' behind your gate drive you needed.

#### T3sl4co1l

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##### Re: Explaining Gate Capacitance vs Gate Charge?
« Reply #6 on: September 19, 2020, 03:38:42 am »
Charge doesn't vary with resistance, but you've got everything else.

Selection, then:
- Meet or exceed Vds(max), obviously.  Pick at least 20% overhead on supply maximum.  Example: JP/US-only, mains powered, half-bridge inverter.  Mains is 120VAC, rectified is ~160VDC.  Choose 200V or higher rating.
- Rds(on)(max) is determined by permissible power dissipation as conduction losses (which depends at least in part on the application)
- Don't worry about Id(max), it's a reference value that depends on thermals.  For example, the same die in a TO-220AB might be rated for 200W and 35A, and in a TO-220FP only 30W and 14A.  Both parts have identical Qg, Vds at a given Id, etc.  The one just can't dissipate as much power because of the package.  Or compare the TO-220AB to the D2PAK, which often have exactly the same ratings (a D2PAK is a TO-220 with short tab and SMT formed leads), but good luck bolting a D2PAK to a heatsink.
- Select package (depends on application)
- sort by Qg and price (smallest first)

You obviously need to add switching losses to the total power dissipation; this isn't the easiest to calculate, but it can be estimated, and usually less power is dissipated thanks to the steep Coss(Vds) curve that tends to shift the switching rate in your favor.

You will often find very old parts (e.g. IRF(P)xxx) that have awful specs (comparable or even worse than the above example!), but are gobsmackingly cheap.  This can be worthwhile, just depends on the application.  Obviously you aren't going to be setting any speed or efficiency records with them.  If that's fine for the application, there you go.

Note this is for switching duty only.

For linear application, you need a wide SOA, high power dissipation, and low capacitances (or charge) are needed where bandwidth is important.  Rds(on) probably doesn't matter, as the point of linear applications is to spend most of your time above the resistive saturation region.  Obviously, if you have some minimum operating voltage, and maximum current, that defines a maximum resistance, which can be used for selection.

Parts are rarely if ever filtered by SOA, so expect to spend a lot of time flipping through datasheets.  PITA, but so it is.

As I mentioned earlier, high power dissipation goes with large die area, which can actually be a feature rather than a bug for those old parts!

A note: lack of DC SOA curve isn't a guarantee that that particular mfg and part is unsuitable for linear operation.  Only way to really be sure is get some and test.  (But if you see steep cuts even in the 10 or 1ms curves, I wouldn't bother.)  This can also be nice about old parts: if they're using the same old design, the die is probably huge, and the low power density means more freedom from runaway failure.  I've tested a new Vishay/Siliconix IRF740PbF to something like 150% of its claimed rating, which really just means that, they've rated it with RthJC(max), while the actual value happens to be much better.

Amazingly, despite the new SuperJunction designs having smaller die size than ever -- a lot of them do offer DC SOA.  Don't usually get as much max power, again because of the small die, but if it's enough, and the price is right... sure, why not?  (FYI, FQA9N90C is one of the best watt/\$ I've seen, in higher voltage ratings.)

And, to sum up the dynamics -- the figure of merit of a transistor is how much it can do, in what time.  That is, more Vds, less Rds, and less Qg or C, are all desirable.  This affects both switching and linear applications.  You might only need so-and-so performance for a given application, and that's fine.  If you need to push the envelope of what's possible, search along these lines.

There's more to choose from along these lines; RF MOSFETs, and SiC and GaN MOS/FETs, are all available for higher speeds.
- RF MOSFETs have significantly reduced capacitances (and less nonlinearity, i.e. smoother C(Vds) or C(Vgs) curves), and relatively generous power ratings, at the expense of Rds(on).  Packages range from TO-220 and 247 to SMTs and wide microstrip packages, with bandwidths from 100s MHz to the low 10s GHz.  Not very useful for switching, the Rds(on) is unimpressive, nevermind the cost.
- SiC MOSFETs have higher Vds(max) and lower Rds(on), with the downside that the drive voltages are higher (typically +15/0 to +20/-4V -- yes, some need negative off voltage).  Power dissipation isn't fantastic (the dies are amazingly small!).
- GaN has modest Vds(max) (topping out at 200-600V in various families, with a few pushing 900V now), and incredible speed.  GaN has long been used in RF applications (10s GHz+) but it's relatively new in power switching.  It's scary how fast these are: Qg of 10nC might get you a few kVA of switching area, and it'll swing it in one or a couple nanoseconds.  Specialized packages (typically DFN style SMTs), on multilayer PCBs, are all but obligatory.  Every millimeter of stray conductor length is series inductance working against you; layouts are critical!  Dies are very small, and not robust (no avalanche ratings, low Vgs(max)), N/A for linear application.  Low gate drive voltage is simultaneously a blessing and a curse: again, layout is critical to avoid feedback.

Also IGBTs, primarily for switching (I have actually seen some with DC SOA though, which is scary; IGBTs are even higher power density than MOSFETs!).  Same idea, select based on conduction losses, gate charge and such.  Key difference: Vce(sat) is more like a diode drop, typically 1-3V at rated current, depending on voltage and speed grade (there's a tradeoff there, of course).  They're available in speed grades; use the one appropriate for the application.  (They don't switch quite like MOSFETs: they remain on for a little while after removing gate charge.  So the turn-off losses are less dependent on R_G, which at least means you can get away with a smaller driver.)

Also also, another interesting quirk of IGBTs, and SJ MOSFETs: they tend to saturate in load current, under short-circuit conditions (i.e. at high voltages -- in linear operation).  That is, as you keep increasing Vg(on), while forcing Vds/Vce to stay high, Id/Ic tends to level out at some point.  Which makes them somewhat less great for pulsed power applications (you can't get any more than Ipk * Vds(max) switching area, under any condition), but also makes them somewhat more robust under fault conditions.  (Protip: add a desat detector circuit, to detect such a fault and turn off the transistor within a few microseconds.  You'll blow up a fraction of the parts you would otherwise!)

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!

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