Fabrication your own chips

[ali_asadzadeh]

Hi,
After years of working on Smart grid industry, I think my VHDL design on a Xilinx FPGA would be ready under 3 months for prodcution,And I think it would make a lot of sense to build it into an ASIC. my design clock is around 120MHz, Also i have a very limited budge, Under 10K$ and I want to manufacture around  at least 1K units for the first run. After some random search on the net, I found this PDF with real prices on that.

https://europractice-ic.com/wp-content/uploads/2020/02/General-MPW-EUROPRACTICE-200212-v5.pdf

Also We have seen Chinese techs like padauk semi! with 0.03$ MCU's, So I asked myself why not give it shot!

The lowest price from this PDF is from on semiconductor for 0.7u node, it's around 300ERU for 1mm area! can my design reach 120MHz @ 0.7um?

my current design can fit on a 50K lut FPGA from xilinx (ARTIX 7)

So my question is this, Can my dream be come true? what about Chinese companies?are you aware of one? can we achieve it?

Any Ideas are welcomed

[hans]

I know europractice as a facilitator for academic research (universities) in IC design, which need low-cost (e.g. almost 'free') access to tools (e.g. Cadence, Synopsys) and new IC technologies.

I'm not sure if this pricelist is realistic for companies. I don't have experience with pricing in industry, but I imagine them to be far more expensive. For one, ICs of multiple research projects are usually pooled and large research groups may only send a couple of tape-outs per year. Then, these pricing may also only limit an one-off design, where the real intent is prototyping, design&simulation verification such that the novelty can be published in IC conferences or journals.
Some of these price lists may not include packaging. I've seen a colleague working on a rather large IC requiring a fairly large package (>=100pins), and I think his packaging fee for a couple dozen chips was half your budget.

Also 0.7um is quite old, like dating back to the early 90s. The Pentium chips of that era ran 60-100MHz on that technology.

Honestly I think a 1K volume to replace an FPGA is too low. Most figures I hear being tossed is a volume of 10 to 100K+ for an ASIC to make sense.

[ali_asadzadeh]

Thanks for the info, 10K is huge in china market, also you can find many things about 5 to 10X lower prices in china, I wonder what fabs or tech the paduk use! so with my budget we can buy around 330K units of their MCU in single unit price
I think something between 350 to 180nm may have very good prices there, our Chinese friends may shed some light on us,and If I can make 10K to 100K with my budget,I would do it without a doubt!

Besides nobody works for free,even for universities! they certainly make 50% profit on these prices,so they can keep it like this.

[SiliconWizard]

For such low quantities, your best bet would be those MPW services such as Europractice, but there are others worldwide.

Your main issue cost-wise will be getting access to the development tools (such as Cadence/Synopsys) and the PDK for the choosen CMOS process.

If your ICs contain only logic, there are services that can do this for you - you essentially give them the HDL, with a few back-and-forth with them to fix some potential issues, and they do the rest. Likely to be more cost-effective, unless you have access to the required above tools already (for instance through some university - but usually it's not possible for commercial uses.)
(Note there are also services for full mixed-signal designs, but that's a lot more expensive.)

There are independent (fabless) design services like this, and some semiconductor vendors also provide one, such as On Semi: https://www.onsemi.com/PowerSolutions/content.do?id=16788

And of course you still need to make sure this is worth it for just a few hundreds or even a few thousands ICs.

[sam[PS]]

I don't know if they still do that but few years ago ALTERA offered a semicustom ASIC service where you could develop your design on some of their FPGA then when you are happy with it you just send them your design files and they build semicustom chip for you. I believe it's just the same fpga fabric without the programmable interconnections, they just hard wire the connexion on the top copper layers.

Anyway in your case i think it worst checking they still offer it.

Just my 2cts...

[TheUnnamedNewbie]

Another thing to point out: How large is your design in terms of gates? Does it need more modern technolgies (60nm ro lower) to be reasonable? If so, 10k is just not gonna cut it, the minimum-area requirements of MPW services such as Europractice will still blow way past that budget. (10k won't get you even a single mm2 of die area in anything past 60nm, and you usually need 5-6mm2 or more). I'm an analog designer so I have no idea if your design would fit on .7 um technologies.

Also keep in mind that these MPW services don't give you volume - with europractice, depending on the foundary (TSMC, GF, ST, ...) you get 40-100 samples. Great to test a design or for research, but if you have to get your cost of production out of those 100 samples, you are gonna have to charge over 500-600 euros a sample *just to make back the MPW cost*. This does not include testing, packaging, distribution, etc. In other words, great to get silicon in hand to test (and perhaps to go to investors) but not a viable product path.

Also, the discounted tools through Europractice, to my knowledge, are only for University/non-profit research institutes. If you want to sell a product, you are gonna have to talk and deal with Cadence/Synopsys/Mentor yourself. I do believe they have plans where they offer software for very low prices for the first few years to startups (so you can get through seed investing and get a decent prototype etc as startup without having to spend 80% of your capital in a few Cadence licenses). They ofcourse factor that in to the long-term pricing...

[ali_asadzadeh]

Thanks for sharing, I wonder if Chinese companies would build parts for us too. So maybe I could find them, this is the best option I think, and they will give you their software for free too.

[excitedbox]

Those are prices for test chips. You get 20-100 samples of your chip for that price depending on which fab they are produced at. The quantities also seem to change each year. If you want to get a chip made you need to calculate the area of your chip in square mm times that price. I didn´t check if you had the Academic discounted price or the business price.

They group together a bunch of projects and put them on the same wafer to share in the cost for making masks. That is not what it costs for large quantities. There are companies doing mixed wafers in larger quantities but you will be limited on repeat ordering.

There are mask less processes that may work at that scale which use UV projectors but they are not as popular because of the slower speed. They do reduce the upfront mask cost though. Mask cost up to 1000 each and you need a lot of them. Some chips use 50+ masks depending on complexity and node/size.

A 300mm wafer full of chips will cost about 2-3k at 0.7u but the masks will cost more than your budget is. Upside is that once you have the masks you can produce tons of wafers.

Don´t forget chip packaging costs. Just a silicon die is pretty useless without pins to solder to your pcb. Those can cost a few pennies up to several $. I was recently quoted 18cents each for a 80sqmm chip in 1k quantity.

[ali_asadzadeh]

Thanks for sharing, Do you have any Idea for example how padauk can make 0.03$ MUC? where do they make them?

[mikeselectricstuff]

Maybe you should expore the cheap Chinese FPGAs before looking at ASICs