| Electronics > Projects, Designs, and Technical Stuff |
| Fabrication your own chips |
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| TheUnnamedNewbie:
Another thing to point out: How large is your design in terms of gates? Does it need more modern technolgies (60nm ro lower) to be reasonable? If so, 10k is just not gonna cut it, the minimum-area requirements of MPW services such as Europractice will still blow way past that budget. (10k won't get you even a single mm2 of die area in anything past 60nm, and you usually need 5-6mm2 or more). I'm an analog designer so I have no idea if your design would fit on .7 um technologies. Also keep in mind that these MPW services don't give you volume - with europractice, depending on the foundary (TSMC, GF, ST, ...) you get 40-100 samples. Great to test a design or for research, but if you have to get your cost of production out of those 100 samples, you are gonna have to charge over 500-600 euros a sample *just to make back the MPW cost*. This does not include testing, packaging, distribution, etc. In other words, great to get silicon in hand to test (and perhaps to go to investors) but not a viable product path. Also, the discounted tools through Europractice, to my knowledge, are only for University/non-profit research institutes. If you want to sell a product, you are gonna have to talk and deal with Cadence/Synopsys/Mentor yourself. I do believe they have plans where they offer software for very low prices for the first few years to startups (so you can get through seed investing and get a decent prototype etc as startup without having to spend 80% of your capital in a few Cadence licenses). They ofcourse factor that in to the long-term pricing... |
| ali_asadzadeh:
Thanks for sharing, I wonder if Chinese companies would build parts for us too. So maybe I could find them, this is the best option I think, and they will give you their software for free too. |
| excitedbox:
Those are prices for test chips. You get 20-100 samples of your chip for that price depending on which fab they are produced at. The quantities also seem to change each year. If you want to get a chip made you need to calculate the area of your chip in square mm times that price. I didn´t check if you had the Academic discounted price or the business price. They group together a bunch of projects and put them on the same wafer to share in the cost for making masks. That is not what it costs for large quantities. There are companies doing mixed wafers in larger quantities but you will be limited on repeat ordering. There are mask less processes that may work at that scale which use UV projectors but they are not as popular because of the slower speed. They do reduce the upfront mask cost though. Mask cost up to 1000 each and you need a lot of them. Some chips use 50+ masks depending on complexity and node/size. A 300mm wafer full of chips will cost about 2-3k at 0.7u but the masks will cost more than your budget is. Upside is that once you have the masks you can produce tons of wafers. Don´t forget chip packaging costs. Just a silicon die is pretty useless without pins to solder to your pcb. Those can cost a few pennies up to several $. I was recently quoted 18cents each for a 80sqmm chip in 1k quantity. |
| ali_asadzadeh:
Thanks for sharing, Do you have any Idea for example how padauk can make 0.03$ MUC? where do they make them? |
| mikeselectricstuff:
Maybe you should expore the cheap Chinese FPGAs before looking at ASICs |
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