configuring VCO input signal so it will be sensitive in PLL system

[john23]

Hello,I have made of a system which is based on the article attached.
I tuned the YIG to the resonance of the resonator, then i measured the output of the IF on a scope as shown below.
When I tuned to ph2 pase shifter i see the "error voltage" level shanges which need to go back to the YIG "FM" port as shown below.
Also i need to make sure that the signal going back to the YIG is something which the YIG could make changes so It will be sensitive to the signal.
How do i need to tune the phi2 phase shifter so I wull get a lock in the resonance frequency?

https://www.artisantg.com/info/Avantek_AM_4060M_Manual2_201622493619.pdf

[jwet]

I assume you're aware that the figure is from a '04 paper by Gupta et al.  You can access it on research gate.

Paper-
High Spectral Purity Microwave Oscillator: Design Using Conventional Air-Dielectric Cavity

Amitava Sen Gupta, Senior Member, IEEE, David A. Howe, Craig Nelson, Archita Hati,
Fred L. Walls, Fellow, IEEE, and Jose F. Nava

Possible Help from paper-
description of  phase shifter 2 in the operation section-

The amplified output is supplied to one port of the phase detector, a double-balanced mixer (DBM), and the other port is given a reference signal in phase quadrature with the first. Phase quadrature condition can be easily obtained within an error of 1–2◦ using the mechanically variable phase shifter φ2. We simply use
voltage null out of the mixer as our criterion for the phase quadrature between the two inputs. This is because our mixer is a carefully chosen one that has very well matched diodes. This ensures that the YIG oscillator AM noise-to phase noise conversion is not a significant factor compared to the thermal noise floor.  I don't know if this helps- I don't fully understand it all just thought it was interesting.  Low phase oscillators like this are used in spectrum analyzer LO's to move chunks of spectrum without contamination- I've played with these before during repair work.

[john23]

Hello Jwet, this is very intresting what you are saying, I attached the article.
I  have a mixer which output something close to DC signal this signal goes into an amplifier which amplifies the signal.
The amplified signal goes back into the YIG.
The amplified signal is suppused to be the guidance for the YIG to "FIX" the situation and shifting the frequency in the other direction.
What do i need to check in the signal which goes in the servo amplifier(the output of the mixer)
How can i make sure there will be dinamics of fixing the frequences.
Thanks.

[jwet]

The signal at the bottom of the block diagram isn't an "IF", it is the PLL error signal- the mixer there is the phase detector, the whole thing is a PLL.  As with all PLL's, the the integrated signal after the servo amplifer will drive the YIG (A VCO) into line.  The phase detector (mixer) should produce a minimal signal when the loop is locked.  That's about all I can tell from the paper.  Contact the paper's authors, its 20 years old but they're probably still out there.

[john23]

Is there some strategies regarding the lock?
Thanks.

[jwet]

You can sense lock by looking at VCO input at YIG, AC coupled it should very quiet and want to return to quiet after you move something, like a small phase adjustment.  You're just sensing that the loop is really closed.  If you want to get fancy, you could look at VCO input with a spectrum analyzer- anything there will turn into residual FM, etc.  The Bible of PLL's is Gardener's PLL Techniques.