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Failsafe P-FET gate drive?

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LogicalDave:
I'm designing a circuit that uses low Rdson P-FETs to switch 24V power at moderate current levels (5-25A).  The FETs have 3-5mOhm Rds when Vgs is between -5V and -12V so thermal dissipation is minimal. Vgs max is -12V.  Switching is infrequent (this is a relay replacement application not an SMPS) so I don't need a high current (fast) gate drive. 

I can easily achieve this with a resistor pulling the gate to the source voltage (24V) and a 15V zener diode from the gate to ground.  This keeps Vgs at (15-24= -9V) and the FET saturated.  This works well, but a problem arises if the power supply sags under load: because the zener voltage is constant, Vgs will drop linearly with the supply voltage and if it drops below -5V, the FET will fall out of saturation causing Rds to rise and the FET to overheat and fail.

So the question: other than a brute force solution using several op-amps, has anyone seen or designed a clever, simple, failsafe, P-FET gate drive circuit (or reasonably priced integrated driver) that maintains good Vgs (e.g. -10V) even if the source voltage drops, and shuts off the gate drive if Vgs becomes too low to maintain saturation?  Thanks!

AndersJ:
Perhaps a voltage supervisor such as a MCP120 can be used to detect low Vgs and turn off gate drive.
A zener would be needed to protect it from overvoltage.

Ian.M:
If you drive the gate from a switched current sink, the drive voltage is set by the product of the current and the gate pullup resistor, provided the sink has enough headroom, so you can limit the maximum gate drive.  The problem then reduces to disabling the current sink when there's insufficient headroom, for which, AndersJ's suggestion of a voltage supervisor will do nicely.

However, assuming there's a regulated logic supply rail available, and the control signal is a rail-to-rail logic signal, a fully discrete solution is reasonably practical.  See attached LTspice sim.

N.B. you only need ONE lockout circuit for a number of switched current sinks and associated P-MOSFETs.

LogicalDave:
WOW.  Thank you soooo much Ian.M; I can see why you are named a Super Contributor; I think Dave needs a new category for folks like you (Super-Duper?)

That was not just a concept, but a clever circuit and complete SPICE simulation; simply amazing!!!

If I understand correctly, I'd only need to duplicate the PFET (M1,R6) and control current-sink (Q2,R7) to fail-safe drive additional loads (my circuit actually has 3 such loads).

Many thanks Ian!

Ian.M:
Yes.   However the MCP120 voltage supervisor AndersJ suggested vastly simplifies the circuit and also removes the dependency on the logic supply voltage for UVLO (but not for the sink current that sets the drive).  Replace R3-R5, Q1, Q3 with the MCP120, fed from the R1:R2 potential divider.  Reduce R1,R2 for a greater divider current as the MCP120 needs up to 60uA supply current.  You'll also need to pick a divider ratio and MCP120 trip-point variant to get your desired UVLO threshold while ensuring that MCP120 Vdd doesn't exceed 5.5V in normal operation and 7.0V abs. max.

There are plenty of alternatives to the MCP120 - all you need is a comparator with integrated reference, that will either run from your logic supply (open drain or push-pull), or an open drain one that will run from your max. main supply or draw a low enough supply current that you can power it from a potential divider.

If you stick with my BJT idea you'll need to do some worst case analysis to confirm that the UVLO trip point is acceptable and that R5 provides enough hysteresis over your full working temperature range and no matter how component tolerances stack up.  hFE variation from part to part and  Q1 VBE variation with temperature are likely to be the main issues.

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