Aaaand, all together for the people at home: <attach>
I noticed the CLC filter part changed slightly between screenshots so, mentally stitch together whichever part of that applies. Looks to be just simplified labeling and better condensed wiring, but there is a cut off something-pin-22 in the one, absent elsewhere?
Interesting, using a window comparator when the chip has UVLO already; maybe for higher accuracy? Else, just the OV would need to be added (perhaps using a single LM397/TL331?).
Can you share the layout (particularly around the inverter)?
Thanks for your inputs. Interesting about the gate-to-source capacitor. I would figure the larger effective Ciss/Cgd ratio would be beneficial to keeping the from some sort of dv/dt induced turn-on? So, what oscillation mechanism are you talking about?
Nah, not a transient problem, unrelated. Only during turn-on/off, it may oscillate in the 100s MHz.
I agree with you that I think the LT and similar chips have the fault conditions and corner cases better accounted for, and should overall be more robust.
LT4356: https://www.analog.com/media/en/technical-documentation/data-sheets/LT4356-1-4356-2.pdf
RT1720GF: https://www.richtek.com/assets/product_file/RT1720/DS1720-01.pdf
LM5069: https://www.ti.com/lit/ds/symlink/lm5069.pdf?ts=1620320358819&ref_url=https%253A%252F%252Fwww.google.com%252F
Sorry to probe you so much here, but when you say, these controllers are not great for precharging...you mean controlling inrush current into DC/DC input capacitors? Controllers above use a very small turn on current, like 50uA to bring the gate voltage up slowly, through the MOSFET's ohmic/linear region.
Yeah, those. I've used one of them before, might've been the LM5069? Worked fine, albeit with less load capacitance. I see your total is/should be around 560uF, within the realm of possibility I think? The trouble is, if your transistor isn't big enough (in terms of die and mounting base volume), it won't have a big enough SOA to handle precharge by itself. It's hard to find SMTs big enough to do that -- you're basically limited by physical size, DPAK is too small for much of anything, D2PAK is alright but maybe marginal or too small here, D3PAK does exist but takes up more space and cost -- so, YMMV.
Not that that's a problem in and of itself either, as you've got resistors in there -- but the resistors themselves should be protected in that case. Actually I bet you could ab/use one of those controllers
as the resistor, and just put a comparator on the hard switch -- so it pulls in only when the voltages are nearly equalized (within 5 or 10% say). That should be a good enough sign that the load isn't faulted, and the precharge has done its job. Meanwhile, the precharge starts up and tries to do its thing, and if it can't, it just sits there disabled and nothing further happens. Fail safe.
Alternately, use a depletion MOS big enough that it can handle inrush (assuming precharge isn't a required spec), and turn it off for OV. Hm, "big enough" might not exist -- well, if an enh. mode turns on by Vgs(th), at least it's not as jarring as turning on into the full 36V or whatever. So, that'd be basically mirroring the polarity protection part, with the zener clamp (oh hey, that can be the same 9.1V zener from aux, no need for 16, unless that's also used somewhere else?) except also turning it off when OV is triggered.
Oh, OV circuit needs to be ground-referenced to input or the common-source of this back-to-back pair... that's not great. When Q2 is turned off, GND voltage is allowed to rise relative to input GND or the common-source node. Again, maybe not much because the boost is off and resistors are pulling down. But if GND does rise relative to that, then the OV condition can apparently stop, and it starts cycling. (For sure, OV threshold must be below TVS1 clamping voltage; and it looks to be so.)
Hm, what is R9 anyway, it's dual?
It's interesting you made a comment about the gate-source capacitor, as from the LT4356 datasheet, they actually recommend adding extra gate capacitance if you need gate slew rate to be lower:
Want to say I've seen that with an R+C as well. Definitely safer with some damping resistance in there...
I think LT in general, has a bad habit of omitting gate resistors, perhaps assuming that the reader knows better? Not sure.
Anyway, easy enough to review all the stuff
other than what's actually probably going bad... Hopefully some new data can get you closer to your solution.
Tim