Can I use a 640x200 STN LCD controller to drive a 640x240 STN LCD display?

[David00]

I have an old LCD display controller that drives a 640x200 STN LCD display. The interface has Frame Pulse/Frame Line Marker (FP/FLM), Line Pulse (LP), and LCD Clock control lines and D0..3 data lines.

Given the scarcity of 640x200 displays, I was wondering if it could use the controller with a 640x240 display panel. If after sending data for the first 200 rows the controller generates a FP/FLM, will a 640x240 panel simply display the first 200 rows correctly with no adverse side effects from not writing data to the remaining 40 rows? Or will those remaining rows suffer from bias or other issues?

[amyk]

Need to see some datasheets to tell what's going on.

[David00]

I don’t have a data sheet to hand for the controller, it’s an old 82C426 (for driving a 640x200 display). But it’s a standard 4-bit interface, as used by most LCDs prior to LVDS. I haven’t selected a 640x240 display yet. However any old 4-bit (or 8-bit) controller & display using FLM and LP control is representative.

But - knowing how an LCD controller and display works in normal operation - the question asked isn’t likely to be answered by data sheets. As normally you would use a controller that matches the display, or vice-versa, so there are the same number of rows and columns. I’m asking about a scenario outside normal operating parameters.

I’d expect that rows 201 to 240 aren’t being energised. So in theory there is no DC (or AC) across any segments or commons for rows above 200. But is this the case in practice? Does, for example, the effect of the energised planes up to row 200 bleed across to those above 200 over time? This question would apply for any LCD controller using the control signals above with parallel data being used to drive an LCD with more rows that the controller is designed for.

[David00]

For the purposes of anyone answering the question please assume that the interfaces are entirely compatible, except that the display has more rows than the controller is sending data for before asserting FLM and starting with the first row again. I’m hoping someone who has a lot of experience using LCDs can shed some light on what happens to the LCD - over time - when not every row is being driven. Can a residual DC bias effect develop in those extra rows?

[amyk]

I asked for datasheets of the specific display in question because it can help answer more definitively what will happen, but I have a good guess. The row (common) driver is essentially a long shift register which in normal operation has a "1" bit loaded into one end based on the FLM signal and activates each successive row of the display, after all the lines are scanned the cycle repeats. If you shift in another 1 while the first one is still there (in this case, on line 200), and begin drawing the next frame, you will have two selected lines and start drawing the next frame on line 200 as well as 0. What you will see is that the first 40 lines are repeated at the bottom, and with half the contrast since they will be sharing the charge.

[David00]

Ah, that’s a good guess and interesting scenario. I’d always assumed that FLM was connected to an internal reset that ensured the shift registers were clear prior to the start of the next cycle. There is no external reset, so some mechanism has to set the initial state.

I’d looked at a couple of data sheets for larger LCD displays, but of course they don’t drill down to this level of internal detail.

[amyk]

FLM is just the input to the vertical shift register. You need to look at the datasheets of the driver ICs themselves to see this, not just the module datasheet (which might show the connections to the driver ICs.)

[David00]

Understood. Thanks for the help.