Author Topic: Fast optocoupler shutoff  (Read 5380 times)

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Offline matthuszaghTopic starter

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Re: Fast optocoupler shutoff
« Reply #50 on: January 30, 2023, 06:10:05 pm »
But that's rated for 2A (8/20us) and 12kV (ESD, contact). Can you limit currents accordingly?

I think I could with the protection scheme outlined above. I don't really want anything where I'm relying on the TVS too much because that means I'm over-exposing the DUT to a  short condition. But, yes, that TVS will only work if I can limit current enough. If I can't, I'll have to choose something else.

With 50 ohms in series, you'd pretty much be done.  Not quite, as 10uF * 50R = 500us not 20us, but a bigger diode could be used trivially without affecting bandwidth.

I don't get the series resistance at the gate, when it can do much more upstream of the transient protection.  This isn't rocket science, it's basically solved passively this way.

I'm not at all against resistance upstream instead of at the gate. But 50ohms (as stated) is way too much. 10ohms is also too much. 5 ohms would be acceptable but that's pretty much at the upper limit.

But, even if we could use 50R, it's not obvious to me that would totally protect the JFET. Even the TVS I proposed, which has a very low clamp voltage, still clamps above where the JFET gate conducts. Clamp diodes, too, will leave a lot of current for the JFET gate. And, these solutions create a much longer transient than my solution, which is about 25,000 times faster.

Your language makes it sound like this whole thing is glaringly obvious, but that solution (a) fails to meet the noise criteria, (b) probably fails to meet the criteria for minimum disturbance to the DUT, and (c) might also fail the damage protection criteria. If it passes the damage protection criteria it's certainly not obvious to me and I'd like to see something that convinces me that it really does.
« Last Edit: January 30, 2023, 06:38:03 pm by matthuszagh »
 

Offline matthuszaghTopic starter

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Re: Fast optocoupler shutoff
« Reply #51 on: January 30, 2023, 06:15:39 pm »
You're still locking yourself into one limited solution...

Limited in what sense? Sure, there are challenges associated with it, like mitigating noise coupling from the switcher. But, limited suggests to me that it fails to handle certain input conditions, which I don't think it does. Please clarify. Still, I'm more than happy to explore alternatives especially if they're simpler than this solution, which is getting quite complicated.

What's wrong with:
- Series limiting resistor e.g. 10R into bidirectional TVS; TVS capacitance can be used as part of filter capacitance to set bandwidth.

10R adds more thermal noise than I'd like. More importantly, though, this exposes the DUT to a prolonged short and provides significantly less protection to the JFET input, which will now be exposed to elevated voltages and lots of current input for 100s of us. I would expect a JFET gate to be able to handle elevated currents for 10s of ns, but 100s of us seems to be pushing it (again, I will damage test the JFETs to actually make sure they can handle the 10s of ns).

- Current limiting depletion MOS; has low resistance at signal levels, zeners or clamp diodes protect amp.

This is a really neat technique that I wasn't aware of. Thanks for pointing it out!

First addressing zeners and clamps: the JFET gate-source is just a pn junction. This doesn't leave a lot of room for devices to kick in before the JFET gate conducts appreciably. Zeners have soft knees, so anything that steals enough current away from the JFET will likely conduct too much at levels where it shouldn't. This greatly lowers the input impedance of the JFET amp and imposes unrealistic demands on the capacitance of the input blocking capacitor. Clamp diodes have similar issues. They provide some protection, but they're not adequate on their own - they only steal some of the current away from the JFET and so the input still needs to be shutoff. Schottky's do a much better job of stealing current from the JFET gate but lower the input impedance too much.

As for the depletion MOS, I'm still exploring this, but I think the fundamental difficulty is that the steady state gate current needs to be kept quite low. I've heard 10mA per JFET thrown around. I don't know if that's accurate - I still need to test this, but let's go with that for now. I'll be paralleling these JFETs, so assuming the current is equally distributed between them that eases things a bit. Let's say 16 JFETs. Total steady state current then needs to be limited to 160mA. The boundary between conduction and non-conduction for depletion MOSFETs isn't very sharp. So, to adequately limit current will require enough series resistance between the MOSFET channel and any external resistors. I've looked at the datasheets for a few depletion MOSFETs and the total series resistance for those would be too high.

I think using depletion MOSFETs could still be very useful as additional protection by imposing a higher current limit (several amps). This should limit the max current during large current transient events (eg plugging or unplugging a power supply).

- Plain old polarity protection circuit like you'd use on a battery, chain two complementary ones and bias them to +V/-V so they pass from (-V + Vgs(th)) to (+V - Vgs(th)) and shut off outside there.

I'm intrigued by this idea, and hadn't thought of it. There are challenges with it, though, relating to the fact that MOSFETs don't have a sharp boundary between conduction and non-conduction. Additionally, threshold voltage varies from unit to unit and is temperature-dependent. The JFET forward drop is also, of course, temp dependent, but not necessarily in the same way. This makes biasing quite delicate, which I don't like. I'm not convinced it can't work yet, but it's tricky. I measured Rds vs vgs for a SiHD240N60E and I'm not sure that's sharp enough. That's just one FET though, I can look at others, perhaps with lower thresholds.

Code: [Select]
| vgs |  Rds |
|-----+------|
| 4.0 | 2.2k |
| 4.1 | 1.0k |
| 4.2 |  959 |
| 4.3 |  472 |
| 4.4 |  149 |
| 4.5 | 66.1 |
| 4.6 | 32.7 |
| 4.7 | 23.9 |
| 4.8 | 10.5 |
| 4.9 | 5.59 |
| 5.0 | 6.20 |
| 5.1 | 2.05 |
| 5.2 | 1.38 |
| 5.3 | 0.99 |
| 5.4 | 0.75 |
| 5.5 | 0.62 |

- Classic, biased diode-bridge current limiter; bias can be from HV BJTs between supply rails.

I'm not familiar with this. Can you explain further or point me to a resource that explains it?

There's an additional consideration, which is that I still need to switch in a resistor during an over or undervoltage condition. The lowpass frequency cutoff is low enough that the capacitor would take too long to charge or discharge. This resistor can't always be in because it lowers the input impedance too much. This means that I still need something to switch this in. The requirements on this aren't too tough (and a simple window comparator would do), but I guess my point is that it still needs to be here, so none of the above solutions are sufficient in and of themselves.
 

Offline matthuszaghTopic starter

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Re: Fast optocoupler shutoff
« Reply #52 on: January 30, 2023, 06:47:50 pm »
What about a dedicated optocoupler to turn off the power MOSes fast?

This is my current solution, or at least very similar to it (see messages above). Rather than optocouplers though I plan to use an isolated gate driver (eg UCC21530). The main difficulty with this solution, in my opinion, is the required isolated power supply, which is horrendously noisy. I think it will be possible to resolve this in an adequate way, but that remains to be seen.

Optocouplers that don't require an isolated supply are what I investigated initially. A lot of people pointed out that won't be fast enough. I'll still measure how fast I can shut it off by placing multiple in parallel and adding a bleed resistor (see first couple messages), but I'm willing to accept this is unlikely to work in the way I originally hoped.
 

Offline inse

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Re: Fast optocoupler shutoff
« Reply #53 on: January 30, 2023, 07:20:09 pm »
I thought it like this: one photovoltaic isolators as now for turning the MOSFETs on and a fast optocoupler to short the gate to source.
Only needs a inverter on the primary side
 

Offline matthuszaghTopic starter

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Re: Fast optocoupler shutoff
« Reply #54 on: January 30, 2023, 07:48:56 pm »
I thought it like this: one photovoltaic isolators as now for turning the MOSFETs on and a fast optocoupler to short the gate to source.
Only needs a inverter on the primary side

Can you recommend a fast optocoupler to short the gate to source? I haven't found anything suitable.
 

Online shapirus

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Re: Fast optocoupler shutoff
« Reply #55 on: January 30, 2023, 07:58:33 pm »
Can you recommend a fast optocoupler to short the gate to source? I haven't found anything suitable.
When I looked for something to isolate an SPI communication path, the best I found was 6N137: approx. 100 ns, give or take, propagation plus fall time.

I too wonder if faster optocouplers exist, but I doubt it. There's probably a good reason why faster isolators are based on magnetic or capacitive coupling principles rather than optical.

p.s. at this point it might be worth it to do some experiments and see what you can achieve in hardware. Sometimes one can find out that something previously rejected can be quite suitable after all.
« Last Edit: January 30, 2023, 08:01:56 pm by shapirus »
 

Offline matthuszaghTopic starter

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Re: Fast optocoupler shutoff
« Reply #56 on: January 30, 2023, 08:12:24 pm »
I thought it like this: one photovoltaic isolators as now for turning the MOSFETs on and a fast optocoupler to short the gate to source.
Only needs a inverter on the primary side

Actually, I'm not totally sure I follow what you're envisioning here. All fast optos I've seen require a supply on the output side. Are you suggesting that I use the photodiode output (from the turn-on opto) to power the fast opto, which, when triggered, shorts that to ground? Does this work?
 

Offline matthuszaghTopic starter

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Re: Fast optocoupler shutoff
« Reply #57 on: January 30, 2023, 08:16:57 pm »
When I looked for something to isolate an SPI communication path, the best I found was 6N137: approx. 100 ns, give or take, propagation plus fall time.

I too wonder if faster optocouplers exist, but I doubt it. There's probably a good reason why faster isolators are based on magnetic or capacitive coupling principles rather than optical.

p.s. at this point it might be worth it to do some experiments and see what you can achieve in hardware. Sometimes one can find out that something previously rejected can be quite suitable after all.

Interesting, that delay for the 6N137 is a bit slower than I would have thought from the typical numbers on the datasheet. Did you have a fair amount of load capacitance in your case?

As for doing the actual experiments, yeah I totally agree. I'm still waiting on a few things before I can but then I will. Not that I'm at all hopeful, but I'm still curious how fast I can shut off the VO1263 by throwing a bunch in parellel and adding a bleed resistor.
 

Online shapirus

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Re: Fast optocoupler shutoff
« Reply #58 on: January 30, 2023, 08:30:16 pm »
Interesting, that delay for the 6N137 is a bit slower than I would have thought from the typical numbers on the datasheet. Did you have a fair amount of load capacitance in your case?
I really have no idea how much of a capacitance there was. The optocouplers were driving GPIO pins of a single-board computer in one direction and CS/MOSI/CLK pins of an ADC chip (MCP3204) in the other. It worked at 2 MHz, but I abandoned this idea because of the extra power consumption of the LEDs and the pull-up resistors on the output side, not to mention the number of discrete components necessary. All of this was replaced by a single ADuM2401 chip designed specifically for this job, but your case appears to be different from isolating digital lines.

(also, the 100 ns that I mentioned are directly from the datasheet, only I used max, not typical -- I did not actually measure it.)

Regarding the use of an optocoupler to flush the gate charge, I think something like the following was assumed:



LED turns on -> transistor opens -> gate capacitor discharges.

(this is actually an interesting idea, I never tried it, but I did experience the problem of speeding up the turn-off of a transistor, let us know how it goes if you decide to try it.)
« Last Edit: January 30, 2023, 08:36:11 pm by shapirus »
 
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Offline inse

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Re: Fast optocoupler shutoff
« Reply #59 on: January 30, 2023, 10:02:44 pm »
Yeah sorry, maybe the idea wasn’t thought to the end..
I didn’t expect that there were no optocouplers with faster turn-on time available without secondary supply.
 

Online T3sl4co1l

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Re: Fast optocoupler shutoff
« Reply #60 on: January 31, 2023, 02:29:11 am »
Limited in what sense? Sure, there are challenges associated with it, like mitigating noise coupling from the switcher. But, limited suggests to me that it fails to handle certain input conditions, which I don't think it does. Please clarify. Still, I'm more than happy to explore alternatives especially if they're simpler than this solution, which is getting quite complicated.

My first objection is more semantic than practical: it's suggestive of "if-then" procedural thinking, which doesn't map well onto analog circuits.  Embrace the continuum!  If voltage goes outside of bounds, don't switch it off (what if switching it off causes voltage to rise further? or reverse so it oscillates?), just increase current, diverting it away from your load.

The practical consequences come when considering marginal cases.  What if the input is extremely noisy (some volts of AC)?  Well, on a practical note, your amplifier is useless (driven to clipping), so maybe it doesn't matter.  But randomly activating (and at a high rate) that switch logic won't do any favors for signal distortion, or time dependency of the response.

A simple clipping filter has the benefit that it's not time dependent.  It's there only when needed and goes away seamlessly.  Distortion increases in an orderly fashion as signal level approaches the threshold.  The onset of clipping is easily recognized in the response.

The linearized version might be interesting to ponder, but isn't going to be easy to pull off (you need to synchronize the transfer curves of two switches, potentially while level shifting).  That is, suppose the switches were adjustable resistors instead; or some kind of V(I) characteristic curve anyway, since we're using transistors here.

Notice also you're making a negative resistance input characteristic: as voltage rises, current falls [suddenly].  This might not be well-behaved say with a reactive source.  Or maybe it's balanced by the shunt switch, but again, it needs to track properly.  And it needs to have the same response rate (control theory is involved too!), lest it have an impedance peak that causes ringing or oscillation (between one or the other "switch" and the source, or any other combination thereof).

Maybe those are equally good reasons to reject the continuum, and stick to a logical method instead. I don't know. :P


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10R adds more thermal noise than I'd like. More importantly, though, this exposes the DUT to a prolonged short

Okay but you're already hot-plugging the thing, what did you expect was going to......nevermind.

(Can't you just plug the thing in, then turn it on?  Normal startup transient / soft-start cycle applies?)


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and provides significantly less protection to the JFET input, which will now be exposed to elevated voltages and lots of current input for 100s of us. I would expect a JFET gate to be able to handle elevated currents for 10s of ns, but 100s of us seems to be pushing it (again, I will damage test the JFETs to actually make sure they can handle the 10s of ns).

Also can always add source degeneration (reduces gain without increasing noise), or bypass the gate resistor with a capacitor (another old school oscilloscope protection feature, does have a long recovery tail though).  (Again, could use depletion MOS for faster recovery while limiting current, I suppose.)


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First addressing zeners and clamps: the JFET gate-source is just a pn junction. This doesn't leave a lot of room for devices to kick in before the JFET gate conducts appreciably. Zeners have soft knees, so anything that steals enough current away from the JFET will likely conduct too much at levels where it shouldn't. This greatly lowers the input impedance of the JFET amp and imposes unrealistic demands on the capacitance of the input blocking capacitor. Clamp diodes have similar issues. They provide some protection, but they're not adequate on their own - they only steal some of the current away from the JFET and so the input still needs to be shutoff. Schottky's do a much better job of stealing current from the JFET gate but lower the input impedance too much.

Well, what's it going to be biased at?  Surely not Idss (Vgs=0) giving minimal dynamic range.  You're already planning on basically a back-to-back diode (SP00R6) (actually I wonder if it's anti-series back diodes* or something, given they show a series diagram internally?) so biasing down a volt or two should be trivial.

*A variant of tunnel diodes, with especially low reverse voltage.  Oh but wait, normal forward voltage.  Or hm, could tunnel diodes be fabricated with just enough negative resistance to compensate for the forward junction?  No that wouldn't make sense, there'd be a shelf in the response. Hmm, maybe they are just punch-through diodes, just tuned for a very low voltage?  Dunno.  Anyway, laughable that they show anti-series zeners as the diagram, they are absolutely anything but.

Also mind, the gate current flows into the channel, which has significant resistance.  It's no rectifier.  Actually it's notoriously poor: consider the pico-ampere diodes, which as I understand it are basically diode-strapped JFETs ala 2N4117.  (Oh, in fact that's exactly their description(!): https://www.interfet.com/pad/ )  Your parallel array will be "stiffer" of course, but Rds(on) will be no less a factor in its response.

So I don't see a need to be picky about a volt here or there.


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As for the depletion MOS, I'm still exploring this, but I think the fundamental difficulty is that the steady state gate current needs to be kept quite low. I've heard 10mA per JFET thrown around. I don't know if that's accurate - I still need to test this, but let's go with that for now. I'll be paralleling these JFETs, so assuming the current is equally distributed between them that eases things a bit. Let's say 16 JFETs. Total steady state current then needs to be limited to 160mA. The boundary between conduction and non-conduction for depletion MOSFETs isn't very sharp. So, to adequately limit current will require enough series resistance between the MOSFET channel and any external resistors. I've looked at the datasheets for a few depletion MOSFETs and the total series resistance for those would be too high.

I would expect ratings to be driven by thermal and electromigration limits, or something to that effect.  10mA is the DC figure.  I would expect pulsed currents of, oh I don't know, 10x for 10s of µs at least, being acceptable.  Compare LED pulse ratings, those can have quite small junctions for example.  I mean, those are in entirely different material too, so take this for the salt-grained hand-wave it is -- but perhaps your testing will find this out.

Mind to do a good number of cycles, like, thousands, or millions even (should be easy enough to set it going in the background and accumulate that kind of time?), on a reasonable range (preferably a dozen parts or more, from various production dates and manufacturers if possible?), and check the small-signal parameters afterwards.  Then re-run at more aggressive settings (higher Ipk, pulse width) until failures are observed.

I suppose noise would be the most critical and least predictable variable here?  I don't have a feel for what it should do.  Want to say it depends on surface states and spooky stuff like that, which shouldn't be affected by forward bias?  Leakage feels more likely to be affected, to me.  Or Vbr, or gm or Vgs(off), those are pretty sensitive and something like spot heating or ionic motion (pushed by high current density?) might do it.

Or just outright failure first (short/open), which seems most likely a fatigue or electromigration sort of mode I think.

Will be interesting to know, independently; post that in a new thread even, if you could. :-+


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I'm intrigued by this idea, and hadn't thought of it. There are challenges with it, though, relating to the fact that MOSFETs don't have a sharp boundary between conduction and non-conduction.

Well so what... think of it this way: you're going from ~100V to 2-4V.  That's a hell of an improvement, eh? :)

Maybe a multi-stage process is needed; but you're already set on that [series and shunt switches] so it's more a matter of how than what :)


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- Classic, biased diode-bridge current limiter; bias can be from HV BJTs between supply rails.

I'm not familiar with this. Can you explain further or point me to a resource that explains it?

Sure,



Any current sink/source will do, this is just shown with R+D bias for simplicity.  Can get closer to the rails with current mirrors (but watch for Early effect!!), or use even just bias resistors if you don't need the currents to cancel out over signal voltages (which is to say, loading the input) (which, really, with a sub-volt range, that should be fine regardless).

Or somewhat higher supplies and generous emitter degeneration, if you need low current noise.  This is the subtraction of current sources after all, their noise will be uncorrelated.


Quote
There's an additional consideration, which is that I still need to switch in a resistor during an over or undervoltage condition. The lowpass frequency cutoff is low enough that the capacitor would take too long to charge or discharge. This resistor can't always be in because it lowers the input impedance too much. This means that I still need something to switch this in. The requirements on this aren't too tough (and a simple window comparator would do), but I guess my point is that it still needs to be here, so none of the above solutions are sufficient in and of themselves.

Okay but what do you need a high impedance for when you're measuring fractional ohm sources?.....nevermind again.

Oh, or is that so you can save on C in the first place?  But that increases noise, at the low end.  Because it's the -- a capacitance is lossless, but the implicit resistance that is always present alongside it, making that filter cutoff -- that has noise, and the noise is effectively filtered by it and there you go.  It's identical* whether you have 1 ohm and 1mF or 1kohm and 1uF.  The only difference is the transition region between those impedances and frequencies, and whatever the high-frequency characteristic should be (apparently very low impedance, to keep voltage noise down?).

*In noise power, but voltage scales with impedance of course, so it's better to use large values here.

Tim
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Offline matthuszaghTopic starter

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Re: Fast optocoupler shutoff
« Reply #61 on: February 01, 2023, 03:22:40 am »
Thanks for the detailed response Tim - I appreciate you taking the time to explain all of this. And I will share the JFET stress testing results when I perform them.

I spent a little time simulating the depletion MOSFET current limiter solution (schematic attached), and I'm starting to like it (thanks Tim!). The BSP149 MOS has 1.7ohm typical (3.5 max) at vgs=0. That's low enough in terms of noise performance and should limit the current to 400mA. Most of that can be diverted through a BAV99 limiter. I'll probably use 2 to limit the current through the JFET gate even further. That decreases the input impedance a bit and adds some capacitance, but it's still acceptable. The ferrite bead dampens the initial current peak. This configuration leaves 80mA current to flow through the JFET gates. With 16 in parallel, I think that should be low enough. I don't know how evenly that current will be distributed between the JFETs, but if it's a problem I can probably add source resistors before each JFET gate (assuming the JFET resistance at the limited voltage is sufficiently low). Another technique I could use if the current is too high is to add a small resistor to the MOS source terminals. Based on the simulation, just 1ohm at each source drops the total current almost in half.

This solution draws a bit more current from the load and for a little longer, but I think that's probably ok. It's also not subject to the initial current surge, even if that was only for 10s of ns.

Obviously, this solution has a huge advantage in that it's much simpler. There are only a few components and they're cheap. And no power supplies are needed. This should also work up to nearly +/- 200 V, which is the MOSFET breakdown voltage, though of course that needs testing.
 


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