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filtering on ground?

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Clear as mud:
I started laying it out the other day.  I think I'm going to use a four-layer board.  I didn't do any fill zones yet except for  a small Vin on on the top layer.  In the area right around the regulator, the top and bottom layers will be PGND, the upper internal layer will be GND, and the lower internal layer will be Vin on the input side and Vout on the output side.  I didn't run any GND traces yet, but I think they're going to connect with PGND right at the big PGND via under the input capacitor.

Clear as mud:
I found an inductor that is actually shielded.  Looks shielded, and says so on the data sheet: Würth 784770100.  $2.64 instead of $1.12 in single quantity.  I will plan on using this one for the output inductor.

winniethepooh_icu:

--- Quote from: KT88 on August 11, 2020, 01:56:39 pm ---Splitting PGND and SGND on the PCB is usually a terrible idea. The purpose of having different ground pins is to avoid current sharing of noisy and sensitive internal nodes through one bond connection (it's not alway just a wire anymore). This is simelar to ADCs by the way...  However it makes sense to treat PGND and SGND differently on the PCB. This means having a parition of the one and only GND on the PCB for PGND and one for SGND. You can find an example in the EVAL-Board layout of the LT7101. The grounds are directly connected but the sensitive signal connections like VFB are separated from the rest of the ground plane. This allows to avoid injecting noise into the fragile parts of the circuit.
It is also a common misunderstanding that a groundplane is able to somehow delete noise that is fed into it... The best results are achieved if no noise is dumped into the ground plane. This can be achieved by taking care of smallest loop areas and proper return paths for transient currents. The most important part is the connection of the input cap for a buck (it would be the output cap for a boost). There is also some significant noise conducted over the winding capacitance of the inductor that has to be taken care of...
If that is done correctly there is not much noise that escapes the regulator circuit....
p.s. The inductor has to be connected with the inner part of the winding to switch node and the outer part will act as a shield connected to the output cap (thus the need for a proper output cap placement and routing...).

Cheers

Andreas

--- End quote ---


+1 to not splitting them.

IMO the actual reason splitting could ever be necessary is because of architectural issues in the IC.   You will encounter some bucks which have internal PSRR issues, noise on the LDO can corrupt internal functionality, you will even find some that strongly depend on the high frequency cap between input and GND being very close to the IC, if not then the high side current sense goes to hell in a handbasket.

As long as the cap on INTVCC is well placed with a tight loop and low impedance to the IC this should be fine.

LT provides reference layouts and if they have EMI data provided with that layout, it is a good hint that the layout is probably good to go.

KT88:
There are two reasons why you don't want to split grounds ever:
1st: You get capacitive coupling of noise from the power section into the control circuit including the feefback amp. This might then look like a PSRR issue (it doesn't mean that there are no poorly designed parts out in the wild that genuinely suffer from poor PSRR performance though...).
2nd: if the IC is monolithic, any voltage larger than 0.3V between the ground domains on th die would cause a current through the shottky diodes violating the absolute maximum ratings for negative voltage referred to grond (although it is not always explicitly stated for differend grond pins like in the LT7101 DS).
This causes two problems: 1st it injects sinificant noise (again) into the control circuit, letting it perform below spec. The 2nd is even more problematic:  this is called electro migration. It comes from overheating of metal traces where the material is physically spreding from it's original location causing potentially both open- and/or short circuits. Depending on the severity of the problem, it can go fast or take even years until the part fails.

The inductor looks good now. Btw. Würth provides models of their inductors for LTSpice. I also would recomment to use more detailed models of the important capacitors. AVX has a pretty comprehensive section on their website called SpiCAT: https://spicat.avx.com . They describe some capacitors as three series tank circuits in parallel. Using these models show even the spikes you get on the real PCB which you won't see in a basic simulation. Doing that it also makes sense to estimate the PCB-trace inductance and add it to the simulation. You could easily run these parasitics as a parameter in LTSpice to get an idea how they influence the noise...you may be surprised that even some pico Henrys can ruin your day...
When you have run the simulation it is a good idea to check the peak current of the inductor and compare it against the data sheet. Important is to consider high teperature saturation current and tolerances. That done make sure you don't come to close to that limits. Saturating inductors are another source of severe trouble...

Cheers

Andreas

Clear as mud:
The layout is mostly done now!  I made a new post in which I included the entire board and not just the 5V switching supply.

If you want to focus on the switching regulator, the last 5 pictures deal with that.  My only specific question, at this point, about the switching regulator is whether I should leave out the GND zone on the layer immediately below the top layer, and just leave it with the two traces surrounded by a PGND zone instead of the GND zone.  I already have PGND zone on the very bottom layer, and on other areas of the first internal layer.

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