Bypass caps for diy z80 single board computer.

[tiltit]

Hi all,
I am in the process of building a Z80 single board computer, the PCB will be home made with the toner transfer method. Currently I have the it working on a breadboard and slowly drawing the schematic.
Of course I will have one bypass cap per IC. I am just wondering what will work out best. 100nf ceramic caps or 1uf electrolytic. It wold be nice to know which would be best and the pros and cons of each type.
Thanks

[deephaven]

100 nF per chip and one 22 uF electrolytic where the power comes in.

[tiltit]

Ok, thanks.
Are there any downsides to overdoing capacitance on the board? Or is it just a waste of money?

[deephaven]

Ok, thanks.
Are there any downsides to overdoing capacitance on the board? Or is it just a waste of money?

Only an increase in power-on surge if you really overdo it.

100 nF is better than 1 uF electrolytic  because you want high frequency decoupling.

[justanothercanuck]

I was using 1uf capacitors on the chips, and one or two 100uf's on the board's power input in my z80 PC/console design.  The bigger the capacitors, the more smoothing they can provide under varying system load (within reason of course).

[daqq]

Ok, thanks.
Are there any downsides to overdoing capacitance on the board? Or is it just a waste of money?

At Z80 and similar speed systems you're OK with 100nF per IC per power pin (taking into account the return path (to GND)) and one or more bulk caps as was mentioned.

While from the logic's point of view you can't "overdo it" with capacitance, from the power supplies point of view you can - both the turn on current and time till rise can be affected (several amps startup current for a few ms). When designing the power supply, take care to take it into account. Also note, that some LDO regulators don't like caps with too low ESR - I'm not sure if it would matter in this kind of board though...

[tggzzz]

Higher value capacitors tend to have higher inductance, and that is definitely not wanted. Small short leads = good.

Make sure you lay out your ground well so as to avoid gaps.

One traditional way with Z80 speed circuits and DIL ics oriented north-south in rows is to run one Vcc and one Gnd track N-S on the topside directly underneath the row of ics. Short connections to the ics Vcc and Gnd are obviously trivial, as is placing the decoupling capacitor. At the top/bottom of the board there are E-W Vcc and Gnd stitching the N-S tracks together, and there are a few opportunistic E-W Gnd signals elsewhere on the board. After those are routed, begin routing the signal tracks.

[tiltit]

Thank a lot guys, I really appreciate it.
I just added the bypass caps to my schematic. If it isn't to much of a bother could someone tell me what major mistakes I have made so next time I can do a little better. I really do not have a lot of experience when it comes to drawing schematics.

[T3sl4co1l]

Honestly, on a breadboard, the shitty signal quality for all those wires dancing through the air will be as bad or worse than anything you can do with the supply.

Back when I was playing with a breadboarded SBC...
http://seventransistorlabs.com/Images/Z80_Timer2.jpg
I had written a PRNG (LFSR type, real easy) into the idle loop, and it would freeze every so often.  Before, it didn't (churning whatever regular cycle of program it was running).  Sometimes hours, sometimes days.

Such is the nature of random: most of the time it's okay, but every so often an unlucky transition (repeating address/data signals, lots of address/data signals transitioning at once, etc.) comes by and whack, out goes...who knows what -- bus state, CPU clock, anything.  I was using a dynamic NMOS CPU, so it required a stable 4MHz clock after reset (it would freeze for, I think, clock below 1.5MHz or so, or above 6MHz -- not much good for overclocking!).  If you've got a static CMOS version, you'll probably have fewer problems like this.

The biggest problems with signal quality are 1. having bad grounds and 2. long traces.  The first is easy to solve on PCB: pour ground on at least one layer, and cut into it as little as absolutely possible (note that anywhere you run a trace through a pour.. you cut the pour in two, the negative space around the trace..).  This is rarely possible, so furthermore, pour the top layer, and via-stitch loose ends as frequently as possible to maintain a solid ground between top and bottom.

Long traces shouldn't actually be a big deal here.  74LS is capable of driving logic-low strong enough to cause some problems on long enough traces (maybe not within a modestly sized board, but if you extend those buses onto ribbon cables, say?), but NMOS and CD4000 CMOS probably aren't.  You aren't using any 74HC I guess, so that's not a worry.  (I would recommend converting CPU signals to CMOS as early and often as possible; it's newer logic, performs better, and saves power.  You'll need 74HCT to interface the CPU, or anything else NMOS/TTL compatible; everything CMOS should be fine as-is.)

As for the circuit, I see oddities:
- Why do you label bus signals on the CPU as normal, then invert them, and call them inverted?  They're inverted from the CPU -- the datasheet indicates active-low states, and the pins on the CPU symbol show the inversion circles.
- IORQ is an output, no?  You're driving it with an inverter (U1A)...
- While you can use a manual reset just fine, you should really have a POR chip (e.g., MCP120-130 range parts -- pick one best suited to the supply voltage, startup delay, and package type you need), so you don't have to remember to manually reset it every time you power cycle.
- I'm not familiar with the INT mode you're using (when I was playing with it, I used the fixed vector mode, INT2 I think it was?), so I'm not sure offhand if that's correct.  The logic seems to be placing an interrupt number (twice the index) on the data bus, which seems useful.  I guess, double check just in case that it's aligned with the correct series of bus signals (IO/MEM, RD/WR, M-states..) and all that.
- Going for an authentic 16550 is fun, but: you're just using it as a USB bridge...why not get a parallel device and be done with it?  Such as FT243R, if I got that right.  Or use an authentic Z80-SIO (and maybe throw in a -PIO for kicks?), though you may have to / want to change your interrupt scheme to use those properly.  A second SIO (of whatever family) would be nice just to have the choice of multiple COM channels; I think there's a dual or multi chip out there..??
- Also, if the CS0-2 inputs on the 16550 are active high, then IO0 needs to be inverted.  Is ADS an input?  It should be pulled to a default state.
- U12 isn't on the master reset?
- Connectors: for best signal quality, every other line should be power or ground (doesn't matter, as long as they're bypassed together).  If not, things can get ugly after just a few feet of ribbon cable, if that's what you'll be using.  It might not hurt to add some ESD protection around there too, if it's going to be hot plugged or whatever.  As long as you have enough local bypass (a few 0.1's and a nice electrolytic -- I'd recommend more like 100uF, but that's fine), clamp diodes would be fine; BAT54S shows up just about everywhere, or you can get a 5V supply, multichannel, ESD chip to save space.  Or if you're avoiding SMT for some reason, hope you like forty diodes in a row...(at that point, to save parts count, you might instead opt for 1N5231 zeners wired from ground).

Tim

[tiltit]

Thank you T3sl4co1l for your input.

You aren't using any 74HC I guess, so that's not a worry.  (I would recommend converting CPU signals to CMOS as early and often as possible; it's newer logic, performs better, and saves power.  You'll need 74HCT to interface the CPU, or anything else NMOS/TTL compatible; everything CMOS should be fine as-is.)

As a mater of fact, there are a lot of 74HC on the breadboard, they where cheaper than the 74LS and I figured that they would work just as well. Maybe that was a mistake?

Why do you label bus signals on the CPU as normal, then invert them, and call them inverted?  They're inverted from the CPU -- the datasheet indicates active-low states, and the pins on the CPU symbol show the inversion circles.

My labels have nothing to do with the "Active low of high". To me it just meant (The original signal inverted). I can see now why some people can find it confusing. Good to know.

IORQ is an output, no?  You're driving it with an inverter (U1A)...

Gosh, silly mistake, thank you for pointing that out.

While you can use a manual reset just fine, you should really have a POR chip (e.g., MCP120-130 range parts -- pick one best suited to the supply voltage, startup delay, and package type you need), so you don't have to remember to manually reset it every time you power cycle.

I will look in to that.

I'm not familiar with the INT mode you're using (when I was playing with it, I used the fixed vector mode, INT2 I think it was?), so I'm not sure offhand if that's correct.  The logic seems to be placing an interrupt number (twice the index) on the data bus, which seems useful.  I guess, double check just in case that it's aligned with the correct series of bus signals (IO/MEM, RD/WR, M-states..) and all that.

Yep, that's interrupt Mode 2 alright, U11 will have the lower 8bits of the address which points to the interrupt subroutine. It works on the breadboard.

Going for an authentic 16550 is fun, but: you're just using it as a USB bridge...why not get a parallel device and be done with it?  Such as FT243R, if I got that right.  Or use an authentic Z80-SIO (and maybe throw in a -PIO for kicks?), though you may have to / want to change your interrupt scheme to use those properly.  A second SIO (of whatever family) would be nice just to have the choice of multiple COM channels; I think there's a dual or multi chip out there..??

I could not find the FT243R but quickly looked over the FT245R that has a parallel interface. It may be just what I need. Thanks for the suggestion.
I have on the breadboard a little bit more than what is on the schematic. There is a 82C55 for gpio and a crude timer circuit generating interrupts that are then reset in the interrupt routine by a 74LS74 flipflop and a 74LS373. I plan to re implement these circuits with extension boards later on. I wold like to build 16 bit configurable timer using a couple of 74LS688 8 bit comparators, binary counters and latches. I know there are some perfectly good timer chips out there, but this is really a didactic project for me.

U12 isn't on the master reset?

Does it need to be?

Is ADS an input?  It should be pulled to a default state.

Oups, I missed that, thanks.

Connectors: for best signal quality, every other line should be power or ground (doesn't matter, as long as they're bypassed together).  If not, things can get ugly after just a few feet of ribbon cable, if that's what you'll be using.  It might not hurt to add some ESD protection around there too, if it's going to be hot plugged or whatever.  As long as you have enough local bypass (a few 0.1's and a nice electrolytic -- I'd recommend more like 100uF, but that's fine), clamp diodes would be fine; BAT54S shows up just about everywhere, or you can get a 5V supply, multichannel, ESD chip to save space.  Or if you're avoiding SMT for some reason, hope you like forty diodes in a row...(at that point, to save parts count, you might instead opt for 1N5231 zeners wired from ground)

I think I would like to keep the design simple, I already have buffers on the buses. You are right in thinking that I will use ribbon cable, but probably not multiple feet of it.

[nctnico]

Higher value capacitors tend to have higher inductance, and that is definitely not wanted. Small short leads = good.

Make sure you lay out your ground well so as to avoid gaps.

One traditional way with Z80 speed circuits and DIL ics oriented north-south in rows is to run one Vcc and one Gnd track N-S on the topside directly underneath the row of ics. Short connections to the ics Vcc and Gnd are obviously trivial, as is placing the decoupling capacitor. At the top/bottom of the board there are E-W Vcc and Gnd stitching the N-S tracks together, and there are a few opportunistic E-W Gnd signals elsewhere on the board. After those are routed, begin routing the signal tracks.

This sounds much like a grid. In my 'DIP days' I used to layout power as a grid as well. However nowadays a 4 layer board isn't that expensive and would offer suberb decoupling.

[T3sl4co1l]

This sounds much like a grid. In my 'DIP days' I used to layout power as a grid as well. However nowadays a 4 layer board isn't that expensive and would offer suberb decoupling.

Rather overkill for this level of circuitry, but if you're going to the trouble -- who needs bypass caps at all: the board itself is literally better than anything you can stick into it!  Just a few ceramics in the corners to trap medium frequencies, and an electrolytic somewhere to dampen it.

Tim

[GK]

As a rough rule a capacitors inductance is proportional to its lead pitch. A small 1uF radial electrolytic capacitor with a 2mm lead pitch can have less inductance than a 100nF ceramic or film (MKT, etc) capacitor with a 5mm lead pitch*. It's a myth that electrolytic capacitors necessarily have high inductance. For example you would never bypass an electro with a 5mm lead pitch with a film capacitor having a 25mm lead pitch.

*But at the end of the day the point is moot if you're bypassing an DIP logic IC with VCC at pin 16 and VSS at pin 8 (just for example) - the track length inductance will dominate, no matter where you put the capacitor in relation to the supply pins and component package.

[T3sl4co1l]

As a mater of fact, there are a lot of 74HC on the breadboard, they where cheaper than the 74LS and I figured that they would work just as well. Maybe that was a mistake?

Ah, well then, that's a good catch!  TTL outputs can't drive CMOS inputs reliably: V_IH(min) is not satisfied by V_OL(min).

74HCT is made with TTL compatible inputs, while retaining CMOS outputs.  So it's good as interfacing.

Again, if your Z80 is CMOS, and everything else (the RAM, ROM and serial I also don't know about, offhand), it should be okay.  Just change the other LS's to HC.

I have on the breadboard a little bit more than what is on the schematic. There is a 82C55 for gpio and a crude timer circuit generating interrupts that are then reset in the interrupt routine by a 74LS74 flipflop and a 74LS373. I plan to re implement these circuits with extension boards later on. I wold like to build 16 bit configurable timer using a couple of 74LS688 8 bit comparators, binary counters and latches. I know there are some perfectly good timer chips out there, but this is really a didactic project for me.

Ah, something like what I breadboarded, back in the day... I tossed on a 16 bit "count to zero" timer that triggered an interrupt.  Good enough to make some reasonable chip tunes, on top of animating an 8 digit 7 segment display with per-digit PWM (the display timing was done in software).

U12 isn't on the master reset?

Does it need to be?

Probably/maybe not, but if the chip itself ever goes bonkers, you have to resort to a power cycle to fix it.  Maybe the power cycle itself is what screwed it up (slow rising supply, dubious voltages / brownout conditions, etc.), in which case it might always happen!

As will be the case with many things in this project... you can always just leave it, and then if it starts going goofy, fiddle with it then.  Or you can "gild the lily" and throw more and more stuff at it.  Follow your heart, I suppose?

Tim

[T3sl4co1l]

As a rough rule a capacitors inductance is proportional to its lead pitch. A small 1uF radial electrolytic capacitor with a 2mm lead pitch can have less inductance than a 100nF ceramic or film (MKT, etc) capacitor with a 5mm lead pitch. It's a myth that electrolytic capacitors necessarily have high inductance. For example you would never bypass an electro with a 5mm lead pitch with a film capacitor having a 25mm lead pitch.

This is partially true, but fails in so many instances that it's "not even wrong", even given the already dubious nature of "rules of thumb"!

Tim

[GK]

As a rough rule a capacitors inductance is proportional to its lead pitch. A small 1uF radial electrolytic capacitor with a 2mm lead pitch can have less inductance than a 100nF ceramic or film (MKT, etc) capacitor with a 5mm lead pitch. It's a myth that electrolytic capacitors necessarily have high inductance. For example you would never bypass an electro with a 5mm lead pitch with a film capacitor having a 25mm lead pitch.

This is partially true, but fails in so many instances that it's "not even wrong", even given the already dubious nature of "rules of thumb"!

Tim

I specifically said a "rough rule" and gave a specific example where it is true that was relevant to the topic of discussion in this thread. I've measured numerous <=10uF low voltage electrolytic capacitors with a 2 or 2.5mm lead pitch that had less or comparable inductance to various 5mm lead pitch film and ceramic through-hole capacitors, but never a 10mm lead pitch electro that could compare! For comparable lead pitch I've found in general that through-hole ceramic is often overrated for low ESL compared to film, but less so for ESR, which I guess goes some way to explaining why ceramic capacitors more often than the other make nice high-Q resonant tank circuits often when you least want it.

[T3sl4co1l]

As a rough rule a capacitors inductance is proportional to its lead pitch. A small 1uF radial electrolytic capacitor with a 2mm lead pitch can have less inductance than a 100nF ceramic or film (MKT, etc) capacitor with a 5mm lead pitch. It's a myth that electrolytic capacitors necessarily have high inductance. For example you would never bypass an electro with a 5mm lead pitch with a film capacitor having a 25mm lead pitch.

This is partially true, but fails in so many instances that it's "not even wrong", even given the already dubious nature of "rules of thumb"!

Tim

I specifically said a "rough rule" and gave a specific example where it is true that was relevant to the topic of discussion in this thread. I've measured numerous <=10uF low voltage electrolytic capacitors with a 2 or 2.5mm lead pitch that had less or comparable inductance to various 5mm lead pitch film and ceramic through-hole capacitors, but never a 10mm lead pitch electro that could compare! For comparable lead pitch I've found in general that through-hole ceramic is often overrated for low ESL compared to film, but less so for ESR, which I guess goes some way to explaining why ceramic capacitors more often than the other make nice high-Q resonant tank circuits often when you least want it.

Well, you said "rough rule", but even your specific example (stated as fact, not also as a "rough" rule, which is what caught my attention) isn't very thorough: a small electrolytic for present purposes might have considerable ESR, so that it's a bad bypass at any frequency -- ESL doesn't even matter.  'Tis a very rough rule indeed when that happens.

It's also noteworthy that electrolytic ESL is generally complicated, so that some advantage can be had using a tantalum, or large ceramic + resistor, even if the average-case ESR isn't much better.

If you compare apples to apples, things get worse; film caps aren't really available below 50V, but that's fine as aluminum polymers are very much equivalent in all characteristics (except cost..).  Needless to say, the combination of low ESR and ESL are significantly below anything a normal electrolytic can muster.  Analogously at high voltages, film caps are often useful to bolster the high frequency ripple capacity of electrolytics, even good performance snap-in types.

Not that absolute minimal ESR and ESL is usually desirable, either; an optimal combination of both is almost always best.

So that's why I said "in so many instances": you practically have to craft situations where the statement remains true.  There aren't nearly enough real examples for it to be useful.

Probably the one place users are most insistent upon it, while being the single most useless application, is in audio amplifier bypass applications.  Seriously, there are "audio quality" electrolytics... in the Digikey catalog no less!

Tim

[GK]

As a rough rule a capacitors inductance is proportional to its lead pitch. A small 1uF radial electrolytic capacitor with a 2mm lead pitch can have less inductance than a 100nF ceramic or film (MKT, etc) capacitor with a 5mm lead pitch. It's a myth that electrolytic capacitors necessarily have high inductance. For example you would never bypass an electro with a 5mm lead pitch with a film capacitor having a 25mm lead pitch.

This is partially true, but fails in so many instances that it's "not even wrong", even given the already dubious nature of "rules of thumb"!

Tim

I specifically said a "rough rule" and gave a specific example where it is true that was relevant to the topic of discussion in this thread. I've measured numerous <=10uF low voltage electrolytic capacitors with a 2 or 2.5mm lead pitch that had less or comparable inductance to various 5mm lead pitch film and ceramic through-hole capacitors, but never a 10mm lead pitch electro that could compare! For comparable lead pitch I've found in general that through-hole ceramic is often overrated for low ESL compared to film, but less so for ESR, which I guess goes some way to explaining why ceramic capacitors more often than the other make nice high-Q resonant tank circuits often when you least want it.

Well, you said "rough rule", but even your specific example (stated as fact, not also as a "rough" rule, which is what caught my attention) isn't very thorough: a small electrolytic for present purposes might have considerable ESR, so that it's a bad bypass at any frequency -- ESL doesn't even matter.  'Tis a very rough rule indeed when that happens.***snip***

What the? I said "A small 1uF radial electrolytic capacitor with a 2mm lead pitch can have less inductance than a 100nF ceramic or film (MKT, etc) capacitor with a 5mm lead pitch."

That is a fact and I've measured it. I pointed this out simply because it is often just assumed otherwise (that the eletcro has greater inductance) and I never even freaking said that the low ESL necessarily* makes the electro a better bypass capacitor, so what is the point of the rest of your lecture?


*Though a highish ESR, on the other hand, can, as a matter of fact, in numerous bypass situations, be in fact beneficial as it dampens parallel/series resonances with track and other bypass capacitor inductances.   





 

[tggzzz]

Higher value capacitors tend to have higher inductance, and that is definitely not wanted. Small short leads = good.

Make sure you lay out your ground well so as to avoid gaps.

One traditional way with Z80 speed circuits and DIL ics oriented north-south in rows is to run one Vcc and one Gnd track N-S on the topside directly underneath the row of ics. Short connections to the ics Vcc and Gnd are obviously trivial, as is placing the decoupling capacitor. At the top/bottom of the board there are E-W Vcc and Gnd stitching the N-S tracks together, and there are a few opportunistic E-W Gnd signals elsewhere on the board. After those are routed, begin routing the signal tracks.

This sounds much like a grid. In my 'DIP days' I used to layout power as a grid as well. However nowadays a 4 layer board isn't that expensive and would offer suberb decoupling.

It is exactly a grid, which is the best you can do on a 2-layer board. The OP mentioned using the laser toner fabrication method, so a 4-layer board would be tricky!

[justanothercanuck]

While you can use a manual reset just fine, you should really have a POR chip (e.g., MCP120-130 range parts -- pick one best suited to the supply voltage, startup delay, and package type you need), so you don't have to remember to manually reset it every time you power cycle.

I will look in to that.

They're really not necessary unless you're trying to save a switch and an inverter.  If you connect the switch to 5v, then output it to the inverter two times to buffer the switch debounce, it's all that's really needed.  Plus, it adds the retro style of having a run/reset switch.  To each their own though, a switch is probably cheaper than a reset chip.

[SeanB]

A lot of Z80 boards used a 555 timer as a reset generator, though they used a 100uf capacitor at the IC pins for decoupling, this often being the main decoupling on the whole board.

If you want to be brave just use 100n disc ceramic 50V capacitors, one per every 4 TTL chips, one for the CPU, and one per 2 DRAM chips. This was done on quite a few boards ( though some ran with only one capacitor on the whole board and the odd 100n every 10 chips or so). To play it safe just put the pads for a capacitor at each chip, you do not have to actually insert the capacitor, on a one or few off you just add as you run into ground bounce or poor logic levels.