Should I route GND and VCC between the signal traces?

[robertbaruch]

So I have this fun 16-bit buffer chip (74LVTH162541):



Notice that GND and VCC are distributed amongst the signal pins which, according to the datasheet, "minimizes high-speed switching noise".

Now, I'm using a four-layer board: top signals, gnd, vcc, bottom signals. If all the signals are now transmission lines thanks to the power planes, will routing gnd and vcc between the signals on the signal layers do anything more for me?

[ahbushnell]

So I have this fun 16-bit buffer chip (74LVTH162541):



Notice that GND and VCC are distributed amongst the signal pins which, according to the datasheet, "minimizes high-speed switching noise".

Now, I'm using a four-layer board: top signals, gnd, vcc, bottom signals. If all the signals are now transmission lines thanks to the power planes, will routing gnd and vcc between the signals on the signal layers do anything more for me?

Tie Vcc to the power plane at each pin and the gnd to the gnd plane at each pin.  Also you need bypass capacitors.  It would be best on each Vcc pin. 

[robertbaruch]

Tie Vcc to the power plane at each pin and the gnd to the gnd plane at each pin.  Also you need bypass capacitors.  It would be best on each Vcc pin.

Thanks for the reply. Let's take it as granted that vcc is tied to the vcc plane and gnd is tied to the gnd plane and there are bypass capacitors.

Also, let's say I want to run the board at 100 MHz with rise times of maybe 1ns.

What I'm asking is if there should also be ground and vcc traces between the signals, in the same way that gnd and vcc pins are between the signal pins on the chips. I'm asking about signal integrity here. Will the transmission lines formed between the signals and the power planes be enough to maintain signal integrity at the speeds and transients I want, or will adding gnd and vcc traces between the signals as they are in the pinouts give me far better integrity -- so much better that I should forego the space taken up by the extra traces.

[robertbaruch]

I found this article where the opinion is that so-called guard traces on a board that already has good reference planes will do nothing.

[Siwastaja]

Extremely minimal additional effect if your stackup already has a ground plane closeby (not on the opposite side, but maybe 100-300 um apart). While there might be some coupling with traces super close to each other (think about 4-6 mil clearance), when you separate the traces enough to actually fit the ground (or well bypassed Vcc; no difference from the AC viewpoint) inbetween, the separation gets so large (e.g., 6+6+6=18 mils) that actually doing the inbetween fills becomes completely irrelevant.

[bson]

What I'm asking is if there should also be ground and vcc traces between the signals, in the same way that gnd and vcc pins are between the signal pins on the chips.

The purpose of the multiple Vcc and GND pins is to distribute the current load for all the output drivers, as opposed to sourcing from a single point. A buffer by its nature tends to switch most or all all its outputs synchronously, with potentially significant loads (buffers are used to drive loads), leading to large transients.  Having multiple power pins makes this more manageable.  I doubt you'll have much crosstalk or other interference at 100mil pin scales.

However, running 0.1" THT with 1ns transition times... I'm beyond skeptical.

[robertbaruch]

Oh, it's SMD, not THT.

[bson]

Ah, heh.  The package looked very DIP/SOIC.

[ahbushnell]

Ah, heh.  The package looked very DIP/SOIC.

It didn't look that way on the data sheet.