JLCPCB 6 layer 2313 stackup confusion

[sink]

Good evening everyone,

I'm working on open source software defined radio based on XC7Z020.
Now I'm thinking about the stackup, and I'm considering 6 layer (top)S-G-S-G-S-G(bottom).
I'm confused, because when i use jlcpcb impedance calculator to calculate 50 ohm SE traces for high speed data, I end up with 21 mils width. It's too much, especially for DDR3 memory. Should I calculate it on my own, in separate pcb calculator?

[ Specified attachment is not available ]

If so, does somebody know the permeability value of core present in 6-layer 2313 type stackup?
I need it to calculate the width of digital traces.

[profdc9]

This calculation doesn't seem out-of-line at least if the dielectric is FR4.  I tried it with Pasternack's calculator and got similar results:

https://www.pasternack.com/t-calculator-stripline.aspx

[sink]

This calculation doesn't seem out-of-line at least if the dielectric is FR4.  I tried it with Pasternack's calculator and got similar results:

https://www.pasternack.com/t-calculator-stripline.aspx

You use 4.2 epsilon_r, and according to stackup, there is one dielectrical core with unknown epsilon_r

[thinkfat]

If possible route the DDR3 traces on the top layer.

[sink]

I don't think it's possible, doesn't matter how hard I will try.
I hope jlcpcb calculator is just faulty.

[thinkfat]

I don't think it's possible, doesn't matter how hard I will try.
I hope jlcpcb calculator is just faulty.

That is not an assumption I'd base a design on.

[profdc9]

In the diagram it says Er1:  4.6, Er2: 4.25, Er3: 4.6.    I would assume that JLCPCB would put the correct values of dielectric constant in their calculator for the JLC2313 process.   Could the actual dielectric constants of the layers be different than these values?

[thinkfat]

I'd just ask them.

[sink]

Thanks everybody, I will ask JLCPCB, and then write what I found out!

[tszaboo]

Now I'm thinking about the stackup, and I'm considering 6 layer (top)S-G-S-G-S-G(bottom).

That could be the problem. Typically a 6 layer board is S-G-P1-P2-G-S, or S-G-S core S-G/P-S

[thm_w]

https://www.eevblog.com/forum/projects/jlc2313-stackup-with-ddr3-fly-by/

[JLCPCB Official]

Good evening everyone,

I'm working on open source software defined radio based on XC7Z020.
Now I'm thinking about the stackup, and I'm considering 6 layer (top)S-G-S-G-S-G(bottom).
I'm confused, because when i use jlcpcb impedance calculator to calculate 50 ohm SE traces for high speed data, I end up with 21 mils width. It's too much, especially for DDR3 memory. Should I calculate it on my own, in separate pcb calculator?

(Attachment Link)

If so, does somebody know the permeability value of core present in 6-layer 2313 type stackup?
I need it to calculate the width of digital traces.

dear sir, JLCPCB will follow up your case. If you need it, you can PM me your registered email. [of course, we will protect your privacy and your design. Thank you!]

[sink]

Hello everybody!

I just figured out what was wrong.
When I select 6-layer board, and inner layer, JLCPCB's calculator assumes, that I want to use as ground reference L2 and L5 - and signal layer L3 - so I would have to leave L4. So instead of S-G-S-S-G-S I wanted and still want to use stackup S-G-S-G-S-G.
The solution is simple. Just use different calculator with dielectric constant values from JLCPCB site
Thanks!