A simpler model might be:

Once the gate driver switches "on", the VDD and OUT pins are connected together with a resistor (Rds(on) of the driver).

This, in turn, connects to the gate, which can be modeled as a series RLC, where R is sometimes given in the datasheet (R_G, gate spreading resistance), plus the driver's equivalent resistance, and whatever external resistance is used. L is also sometimes given, but is better estimated from layout (including trace length up to the driver), and C is the equivalent gate capacitance (use Ceq = Qg(tot) / Vgs(on) -- don't use Ciss, the small-signal, zero-bias parameter!).

The gate also returns to ground, via the source, through whatever impedance the ground path has. This should always be ground plane, if at all possible, so we'll ignore it for now.

Because it's one series loop, any VDD inductance (between main bypass and the chip pin) adds in series with the gate inductance, so we can simplify the circuit further. Likewise, the total bypass capacitance acts in series with the gate capacitance, so it should be fairly large in comparison (if Ceq ~= 10nF, Cbyp >= 100nF would be reasonable, so that the series total Cloop is >= 90.9nF, not much different), but needn't be massive (like 1uF+), unless the gate is as well (e.g., large IGBT modules).

Now that we have all the parameters of this RLC circuit, we can put some braining into it.

When R > sqrt(L/C), it's overdamped, and the transient will resemble an RC charging curve.

When R < sqrt(L/C), it's underdamped, and excess ripple (and oscillation!) will be a great concern.

The time constant is given by approximately sqrt(L*C) or R*C, whichever is larger. The 10-90% rise is about 2.2 time constants.

These simple rules can be derived from the (also still fairly simple) second order differential equation that corresponds to the RLC circuit. On the time scale we're talking (rise time below 10ns, say), there are plenty of other wrinkles that contribute to the overall waveform, but this slower contribution will still be present, so it's still a fair approximation.

Now, since everything's in a series circuit, you might think, those RLC components could be anywhere in that series chain, right? That would be correct. It does not matter. As long as the driver chip's supply does not dip down too low for its own function (usually below 5V, but higher power devices may have a UVLO at a more reasonable 9V or more),

*it doesn't matter how much supply ripple is at the chip.*Indeed, you can see the

*intentionally added supply inductance* at work in this waveform:

This was necessary because the simple yet fast circuit exhibits shoot-through in the pre-driver. To achieve the desired switching speed without burning transistors, some added impedance saves on switching loss, while barely compromising speed.

Dead-bug construction. A discrete CMOS inverter (N and P MOS, gates together), with supply impedance (something like 220nH || 51 ohm), is amplified by an emitter follower, for a cool ~3A peak output current and 12ns rise time. Maximum switching speed about 3MHz.

Tim