Small caps in parallel with large caps: what's the point?

[tggzzz]

From Gauss' law one can calculate that pairs of PCB tracks (or wires) have a capacitance of about 30pF/m. That is valid as long as they are ~5-10x closer to each other than they are long.

Plus an inductance of ~1000nH/m. And the conductor's shape is rather important too at some frequencies.

@fivefish: the impedances of capacitors in parallel don't combine in the way you suggest. A small cap in parallel with a large cap is effectively still a large cap. Folks talking about inherent series resistance and inductance have the right idea.

You can put a capacitor in a spice simulation and simulate its response. It is a shame that no shop stocks such a capacitor. OTOH, you can think of that as an opportunity - all you have to do is manufacture one and you will become as rich as Croesus!

To put it more simply, if you look at the graph provided by fivefish and do the measurement at 1GHz, the "capacitors" are all inductors

[daqq]

From Gauss' law one can calculate that pairs of PCB tracks (or wires) have a capacitance of about 30pF/m. That is valid as long as they are ~5-10x closer to each other than they are long.

Depends on the surroundings. I don't know the exact number, formula, but using Saturn PCB calculator (Great tool by the way!) you get around 0.52 pF/cm and 6nH/cm with a 0.5mm trace width and a plane present 1.6mm under the trace on an FR4 substrate. The tool also gives you crosstalk calculations, impedances etc...

[jdraughn]

Wow, thanks for the lightning fast answers! Sounds like something that would make a fun and instructive experiment to investigate on the breadboard.


The spring-leaf breadboards beloved of amateurs are actually the devil's invention - you spend more time debugging the breadboard than debugging your circuit. Plus the parasitics are awful.

I have had the bad habit of buying the real cheap breadboards and the first few years I was into electronics I had various problems with the poor contacts of a breadboard, but I have gotten in the habit of doubling all power connections with second holes and most of my projects are pretty rock solid now. I can pick them up and move them around without spurious resets, and my analog to digital readings are more consistent.

It's just a small band-aid for some of the issues that crop up using breadboards, but it does help.

[fivefish]

Here's a clearer graph.



and characteristics curve of different type of caps.

[CatalinaWOW]

For all of those trying to calculate trace capacitance and inductance, remember that often the goal of putting capacitors in a circuit is to create a dominant pole so you don't have to worry about those things.  This is the case with the linear regulator circuits which are the most common source of the big capacitor paralleled with a small one circuits.  All of our circuit analysis tools are approximations that are only good under certain conditions.  Therefore successful designers put a lot of effort into making sure those conditions apply.  Those who don't do this spend a lot of time tinkering their circuits into submission, and even more time testing to make sure that they stay well behaved under variations in components and operating conditions.

That is not to say that using trace inductance and capacitance is wrong, just remember that those tools also have limitations and if not well thought out can lead to tinkering and weird field problems.

[tautech]

For all of those trying to calculate trace capacitance and inductance, remember that often the goal of putting capacitors in a circuit is to create a dominant pole so you don't have to worry about those things.  This is the case with the linear regulator circuits which are the most common source of the big capacitor paralleled with a small one circuits.  All of our circuit analysis tools are approximations that are only good under certain conditions.  Therefore successful designers put a lot of effort into making sure those conditions apply.  Those who don't do this spend a lot of time tinkering their circuits into submission, and even more time testing to make sure that they stay well behaved under variations in components and operating conditions.

That is not to say that using trace inductance and capacitance is wrong, just remember that those tools also have limitations and if not well thought out can lead to tinkering and weird field problems.

Very well put and including an excellent signature for some member. 

[SteveLy]

Here's a clearer graph.

From Gauss' law one can calculate that pairs of PCB tracks (or wires) have a capacitance ...

Depends on the surroundings.
...

Good point! In the end one needs to measure things or have things measured. Not because anything is wrong with the theory but because the world is a complicated affair.

[P_Doped]

So you can visualize it...



"when one capacitor’s frequency response is rolling off, another is becoming significant, thereby maintaining a low ac impedance over many decades of frequency."

I don't like this author's approach.  As you can see, the impedance improvement from having all those caps is present  at high frequencies but not substantial.  This issue exists because the author likely used caps from the same family/package and ended up with the same lead inductance (notice how all the cap impedances at high frequency are on the same asymptote).  The improvement possible at high frequency really comes when you take advantage of the fact that a small capacitor can be squeezed into a small package.  Small package <--> small lead inductance.  A better representative graph of the effect you'd like (pardon the quality of the scan) is attached.  Notice the large improvement at higher frequency.

[fivefish]

So you can visualize it...



"when one capacitor’s frequency response is rolling off, another is becoming significant, thereby maintaining a low ac impedance over many decades of frequency."

I don't like this author's approach.  As you can see, the impedance improvement from having all those caps is present  at high frequencies but not substantial.  This issue exists because the author likely used caps from the same family/package and ended up with the same lead inductance (notice how all the cap impedances at high frequency are on the same asymptote).  The improvement possible at high frequency really comes when you take advantage of the fact that a small capacitor can be squeezed into a small package.  Small package <--> small lead inductance.  A better representative graph of the effect you'd like (pardon the quality of the scan) is attached.  Notice the large improvement at higher frequency.

There's a way to reach the author.
Why don't you tell that to engineers at Analog Devices (analog.com)
http://www.analog.com/library/analogDialogue/archives/39-09/layout.html

[JacquesBBB]

Here's a clearer graph.



and characteristics curve of different type of caps.

Please provide the source.

[fivefish]

Impedance/ESR characteristics of caps
http://www.murata.com/en-global/products/emiconfun/capacitor/2013/02/14/en-20130214-p1

And here's an 86 page PDF all about PSU noise suppression and decoupling caps
http://www.murata.com/~/media/webrenewal/support/library/catalog/products/emc/emifil/c39e.ashx

[Votality]

Parasitic series resistance and inductance (due to the construction of the capacitor) prevent the big capacitor from being effective at high frequencies, so smaller (and better at high frequency) capacitors are added to provide effective capacitance over a wide range of frequency.

Yep thats what they taught me at uni

[P_Doped]

So you can visualize it...



"when one capacitor’s frequency response is rolling off, another is becoming significant, thereby maintaining a low ac impedance over many decades of frequency."

I don't like this author's approach.  As you can see, the impedance improvement from having all those caps is present  at high frequencies but not substantial.  This issue exists because the author likely used caps from the same family/package and ended up with the same lead inductance (notice how all the cap impedances at high frequency are on the same asymptote).  The improvement possible at high frequency really comes when you take advantage of the fact that a small capacitor can be squeezed into a small package.  Small package <--> small lead inductance.  A better representative graph of the effect you'd like (pardon the quality of the scan) is attached.  Notice the large improvement at higher frequency.

There's a way to reach the author.
Why don't you tell that to engineers at Analog Devices (analog.com)
http://www.analog.com/library/analogDialogue/archives/39-09/layout.html

Looking at the rest of the App Note, the author does say to put the smallest capacitor closest to the pin, etc.  I think that they understand how mixing different magnitude (and physical size) capacitors will improve the impedance.  He just chose a poor graph to illustrate the point he was trying to make.  If I see him, I'll ask him to revise it.

[T3sl4co1l]

BTW, many caps in parallel typically performs worse than a simple circuit.  The constraint is to have a low power supply impedance; the worst case impedance of your supply network is the greatest offender, not the individual ESR or reactance of the caps.

Namely, high impedances occur at parallel resonances between caps connected in parallel.  This is especially pronounced for long, thin traces between caps, but also beware of resonances with power pours and long traces.

The best solution is not minimal impedance, but optimal impedance.  (Duh?)  Bulk caps such as electrolytic or tantalum (or large ceramic, with an ESR resistor added externally) can be used to dampen the network.  They are not, in fact, being used for bulk energy storage.  Not at those frequencies (>> 1MHz), only damping.  (At lower frequencies, their lower reactance will be more important, such as for power supply filtering.)

For damping purposes, the bulk capacitance should be at least 2.5 times the total bypass on the supply, and ESR about equal to sqrt(Lstray / Cbyp).

Tim

[tggzzz]

I don't like this author's approach.  As you can see, the impedance improvement from having all those caps is present  at high frequencies but not substantial.  This issue exists because the author likely used caps from the same family/package and ended up with the same lead inductance (notice how all the cap impedances at high frequency are on the same asymptote).  The improvement possible at high frequency really comes when you take advantage of the fact that a small capacitor can be squeezed into a small package.  Small package <--> small lead inductance.  A better representative graph of the effect you'd like (pardon the quality of the scan) is attached.  Notice the large improvement at higher frequency.

I have 0603 capacitors ranging from 3.9pF to 10µF, and you can probably get larger ones. The series inductance will be near 1nH, giving a theoretical SRF of ~1.5MHz to ~3GHz

[Siwastaja]

A good, simple real-world example on trace inductance and necessity of several level of power supply capacitors is a MOSFET gate driver. This is because they require very high currents in very short pulses.

Try connecting a gate driver to a large power MOSFET and run it from a lab supply, without a small cap close to the driver, and it will not perform just poorly; it won't probably perform at all, and you'll be able to see overvoltage spikes that can destroy the device.

What happens is this:
Gate driver tries to pump several amperes to the MOSFET gate (which is like a capacitor that needs to be charged quickly). But even a few inches of power supply wire has enough inductance to slow down the current rise, as inductors do. This is seen as a voltage drop; there is voltage over the inductor (the wire). A 12-volt supply may easily drop down to just a few volts, measured by an oscilloscope. The gate driver chip may then enter the Under-Voltage Lockout mode and stop operating. At this point, current suddenly stops, but there is energy stored in the inductance (the wire), and now it is suddenly released, which shows up as an overvoltage spike. It works like a boost converter; the chip "almost shorts" the inductance and when it releases, you have inductive kickback voltage.

Resistance works similarly (voltage drop) but without the overvoltage kickback effect. From stability viewpoint, resistance offers benefits by damping resonances by dissipating power instead of storing and releasing it, but nevertheless it also causes undervoltage transients. Resistance is easier to minimize by just making the trace a big wider, and extremely easy to calculate, but the inductance is the real big problem.

The only solution is to minimize the inductance (and secondarily, resistance) between the power supply and the chip. But the only way to do it is to have the supply physically close to the chip, because the inductance is solely caused by physical distance (the wire length). For this reason, you need to redefine "power supply"; only a small SMD part near to the chip can do well enough. It will be your "local" power supply during peaks. As the average current is small (and spikes are averaged out by the local supply), the wire with inductance and resistance can now maintain the energy level in the small cap very well.

MOSFET gate driver is a good example because it's so simple; you can directly see how much capacitance you need, as the chip just basically dumps energy from one cap to another - from the supply capacitor to the MOSFET gate. MOSFET total gate equivalent capacitance can be approximated from datasheet values, and it is often stated as a rule of thumb that the supply capacitor should be 100 times more so that it doesn't discharge too much during the pulse, which would cause voltage drop - and associated overvoltage peak.

[tautech]

A good, simple real-world example on trace inductance and necessity of several level of power supply capacitors is a MOSFET gate driver. This is because they require very high currents in very short pulses.

Try connecting a gate driver to a large power MOSFET and run it from a lab supply, without a small cap close to the driver, and it will not perform just poorly; it won't probably perform at all, and you'll be able to see overvoltage spikes that can destroy the device.

What happens is this:
Gate driver tries to pump several amperes to the MOSFET gate (which is like a capacitor that needs to be charged quickly). But even a few inches of power supply wire has enough inductance to slow down the current rise, as inductors do. This is seen as a voltage drop; there is voltage over the inductor (the wire). A 12-volt supply may easily drop down to just a few volts, measured by an oscilloscope. The gate driver chip may then enter the Under-Voltage Lockout mode and stop operating. At this point, current suddenly stops, but there is energy stored in the inductance (the wire), and now it is suddenly released, which shows up as an overvoltage spike. It works like a boost converter; the chip "almost shorts" the inductance and when it releases, you have inductive kickback voltage.

Resistance works similarly (voltage drop) but without the overvoltage kickback effect. From stability viewpoint, resistance offers benefits by damping resonances by dissipating power instead of storing and releasing it, but nevertheless it also causes undervoltage transients. Resistance is easier to minimize by just making the trace a big wider, and extremely easy to calculate, but the inductance is the real big problem.

The only solution is to minimize the inductance (and secondarily, resistance) between the power supply and the chip. But the only way to do it is to have the supply physically close to the chip, because the inductance is solely caused by physical distance (the wire length). For this reason, you need to redefine "power supply"; only a small SMD part near to the chip can do well enough. It will be your "local" power supply during peaks. As the average current is small (and spikes are averaged out by the local supply), the wire with inductance and resistance can now maintain the energy level in the small cap very well.

MOSFET gate driver is a good example because it's so simple; you can directly see how much capacitance you need, as the chip just basically dumps energy from one cap to another - from the supply capacitor to the MOSFET gate. MOSFET total gate equivalent capacitance can be approximated from datasheet values, and it is often stated as a rule of thumb that the supply capacitor should be 100 times more so that it doesn't discharge too much during the pulse, which would cause voltage drop - and associated overvoltage peak.

I was told to always hammer the gate, thats the reasons why. ^^^

[T3sl4co1l]

A simpler model might be:

Once the gate driver switches "on", the VDD and OUT pins are connected together with a resistor (Rds(on) of the driver).

This, in turn, connects to the gate, which can be modeled as a series RLC, where R is sometimes given in the datasheet (R_G, gate spreading resistance), plus the driver's equivalent resistance, and whatever external resistance is used.  L is also sometimes given, but is better estimated from layout (including trace length up to the driver), and C is the equivalent gate capacitance (use Ceq = Qg(tot) / Vgs(on) -- don't use Ciss, the small-signal, zero-bias parameter!).

The gate also returns to ground, via the source, through whatever impedance the ground path has.  This should always be ground plane, if at all possible, so we'll ignore it for now.

Because it's one series loop, any VDD inductance (between main bypass and the chip pin) adds in series with the gate inductance, so we can simplify the circuit further.  Likewise, the total bypass capacitance acts in series with the gate capacitance, so it should be fairly large in comparison (if Ceq ~= 10nF, Cbyp >= 100nF would be reasonable, so that the series total Cloop is >= 90.9nF, not much different), but needn't be massive (like 1uF+), unless the gate is as well (e.g., large IGBT modules).

Now that we have all the parameters of this RLC circuit, we can put some braining into it.

When R > sqrt(L/C), it's overdamped, and the transient will resemble an RC charging curve.

When R < sqrt(L/C), it's underdamped, and excess ripple (and oscillation!) will be a great concern.

The time constant is given by approximately sqrt(L*C) or R*C, whichever is larger.  The 10-90% rise is about 2.2 time constants.

These simple rules can be derived from the (also still fairly simple) second order differential equation that corresponds to the RLC circuit.  On the time scale we're talking (rise time below 10ns, say), there are plenty of other wrinkles that contribute to the overall waveform, but this slower contribution will still be present, so it's still a fair approximation.

Now, since everything's in a series circuit, you might think, those RLC components could be anywhere in that series chain, right?  That would be correct.  It does not matter.  As long as the driver chip's supply does not dip down too low for its own function (usually below 5V, but higher power devices may have a UVLO at a more reasonable 9V or more), it doesn't matter how much supply ripple is at the chip.

Indeed, you can see the intentionally added supply inductance at work in this waveform:



This was necessary because the simple yet fast circuit exhibits shoot-through in the pre-driver.  To achieve the desired switching speed without burning transistors, some added impedance saves on switching loss, while barely compromising speed.



Dead-bug construction.  A discrete CMOS inverter (N and P MOS, gates together), with supply impedance (something like 220nH || 51 ohm), is amplified by an emitter follower, for a cool ~3A peak output current and 12ns rise time.  Maximum switching speed about 3MHz.

Tim