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FPGA oddness

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donmr:
They are warnings in the sense that the part may work at some voltages, temps, and clock speeds, and not at others.

Setup time warnings mean the design may not work at maximum clock speed, max temp, min voltage, but may work under other conditions.  You can often slow down the clock to get around these initially.

Hold time violations are not affected by the clock speed and are harder to work around even for debugging.

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