EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: RobertGogol on March 17, 2016, 07:56:47 pm
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Hi everyone,
Polish company Kamami released Altera MAX10 FPGA protoboard based on Arduino pinout called MAXimator :)
I've decided to replace Arduino in my MIDI controller, because I want expand its functionality.
I've never touch FPGA untill today, when replaced Arduino witn new FPGA protoboard.
I've read "FPGA for dummies" and now I'm going to read and watch the rest of Altera's "New to FPGA Resource Center"
I would like to ask you: what should I expect? Will it be much more difficult than programing Atmegas in C with AVRdude and USBASP programmer?
What should I avoid? My major concern is this free version of Quartus Prime will be enough for my project? Or after month of learning and programming I'll stuck and have to pay to use all features of this Max10 FPGA?
How it is to program and configure FPGAs? Is it fun, like playing with 8bit MCUs?
Below you can see a few photos of my controller.
(https://lh6.googleusercontent.com/-knc0yagwI3c/VusK6x9zmuI/AAAAAAAAGI8/NxmjE4bh2BoKZok6oC7lt9RNU2AZX_bPw/w610-h456-no/P3160869.jpg)
(https://lh6.googleusercontent.com/-sbdqxO0TKXE/VusK65nYh0I/AAAAAAAAGJA/4pR6uh-K7VA8NF1Vw1D7Dat5GA16fsChg/w610-h456-no/P3160916.jpg)
(https://lh6.googleusercontent.com/-s1GEvuHkSLo/VusK6nEPIiI/AAAAAAAAGI4/TAsb92DNWAo9DRHhn581ZNTtc7vd-tHCQ/w610-h456-no/P3160923.jpg)
(https://lh6.googleusercontent.com/-CZV-BZZTvUE/VusK7Y3CagI/AAAAAAAAGJE/sHF_0j2UNToh8Djqwgi5UgHkp-WzFoB8g/w610-h456-no/P3160950.jpg)
(https://lh6.googleusercontent.com/-R__7MUNNK44/VusK7lCXWoI/AAAAAAAAGJI/WG9cep0KyAYoHJGBQo5W1q7y77T4s3qJQ/w610-h456-no/P3160956.jpg)
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Distinct shades of VCF3 there....
The key to FPGAs is that you are designing logic, not writing computer code, it is the difference between telling the thing what to do, and telling it what to be, and it is a bigger difference then you might expect.
My rule of thumb is that FPGA design should break things down into blocks small enough that you can draw a logic diagram (As in logic gates, multiplexers and flipflops) for them, at least in outline before you start writing the code.
VHDL is better then Verilog if you are coming from C because it does NOT look like C, subconsciously thinking in terms of C is a nasty trap with C like HDLs.
Some tips:
The action happens on the rising edge of the clock.
Do not gate clocks with logic, instead provide a data valid strobe.
Be careful about sensitivity lists, here be dragons because they can make the simulation differ from the hardware.
Synchronous resets to all registers are a good idea.
Be careful of accidentally inferring latches.
Testbenches are a good and happymaking thing.
Read the family manual to see what templates you must follow to infer things like block rams and other hardware elements.
Have fun.
Regards, Dan.
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The action happens on the rising edge of the clock.
...or the falling edge :D It's the designer's completely free choice, there's no obligation to use one or the other.
Personally I'd advise against trying to draw logic diagrams. VHDL is about describing the behaviour of a system, not the underlying components that make it up, and so you get to skip the error-prone stage of trying to work out what hardware (gates, flip-flops and the like) actually does what you need.
All you need to do is describe how you want the finished device to behave, and the compiler works out how to make that happen using the resources available on a given FPGA.
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...or the falling edge :D It's the designer's completely free choice, there's no obligation to use one or the other.
Personally I'd advise against trying to draw logic diagrams. VHDL is about describing the behaviour of a system, not the underlying components that make it up, and so you get to skip the error-prone stage of trying to work out what hardware (gates, flip-flops and the like) actually does what you need.
On the edge triggering thing, it depends on the part in question, check the part datasheet.
While I agree about writing behavioural code once you have some experience with both FPGAs and with what the synthesiser is likely to do, writing RTL is useful when just starting as apart from anything else the lack of fully constrained timing is possibly less likely to bite you.
Mind you I tend to play with SDR stuff where meeting timing can pretty much mean writing RTL style.
Regards, Dan.
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I've passed thru a few learning videos from Altera, and it looks like
you said guys - I'll have to start from VHDL or other form of description BY WORDS.
What about GRAPHICAL way to do it - just to have a basic bricks like a inputs, outputs
a few functional blocks - actually it should be something like a simulating software (ex. LtSpace) where you build your logic circuit - as I saw it happens in later stage of development process. Fascinating!
Interesting, anyway I'm looking forward to learn VHDL - it looks simple and productive.
Thanks for advice :)