On many PIC18 parts the T0CKI (Timer 0 external clock) input is good for up to 50MHz, given an exact 50% duty cycle squarewave. Add a single fast D type flipflop configured as /2 in front of it, to guarantee that 50% duty cycle, and connect a CCP module output pin to the flipflop /Reset input, to provide the gateing and you've got the makings of a 100MHz frequency counter. If you connect an I/O pin to the flipflop's /Set input, you can pulse the Q output independently of the input signal while /Reset is held low, which allows you to clock through the count stuck in the Timer 0 prescaler at the end of the gate period, effectively increasing the Timer 0 resolution to 24 bits. Given an accurate enough system clock source, (better than +/- 0.05 ppm) that's enough for a 7 digit frequency counter.
If you use a 'classic' midrange PIC16, the max T0CKI frequency is generally considerably lower and you only get an 8 bit timer 0. T1CKI has a lower frequency limit than T0CKI, so using timer 1 to get a 16 bit timer isn't a particularly good option (vs using a PIC18), as its prescaler is smaller so you can only get a total of 19 bits + you need it for the CCP module to produce the gate waveform.
However as others have mentioned designing an analog front end for it to get reasonable sensitivity, and adding an external prescaler for operation up to even 1 GHz requires considerable RF design experience for a reasonable chance of success.