@SiliconWizard
By the way, my circuit is way more power-saving than yours in your post above.
I didn't notice a big difference. The sim gives an average of ~6.6µA with yours at 1.8V, 100MHz, and ~6.4µA under the same conditions with mine.
I pushed mine to 3.3V and 500MHz in the LTSpice file above and get ~80µA. But give it the same conditions as yours and see. Likewise, with yours at 1.8V/500MHz, I get ~33µA, and ~32.4µA with mine. The difference doesn't look significant. And the point was to get it to simulate @3.3V, which doesn't work with yours. But do not hesitate to point out how you figured mine would draw more power, I may have missed something?
That aside, this circuit is basically some form of dynamic flip-flop and can be a bit tricky. Parasitic capacitances are actually part of the design rather than a problem, as long as they are correctly used. It will work properly under a limited range of conditions (including clock frequency and rise/fall times), so, to be used with caution. A quick overview here:
http://www.seas.ucla.edu/brweb/papers/Journals/BRFall16TSPC.pdf