3.3v to 1.0v pulse level shifter

[DenzilPenberthy]

Hi Everyone.

 Has anyone got any bright ideas for this? I've been struggling with it for a while now and I have the distinct feeling that I'm over thinking it and/or missing something obvious.

 I have an FPGA with a 3.3v digital output which can supply at most a few mA. I need to interface this to a device which has a 0 to 1V input which is 50 ohm terminated.

A voltage divider won't do it because the FPGA can't supply the 20mA which the 50 ohm input will draw at 1v. In addition to this it has to be fast, <9nS rise time.

 The device can be physically close to the FPGA but needs to drive quite a long cable on the output so needs a 50 ohm output impedance.

 The first circuit I tried has the problem of the output not quite being 0v when off due to the finite Ron of the mosfet. The 0 to 1v device that it is driving is essentially an analogue device which needs a 'proper' 0v to be fully off.

The second circuit provides a nice 0v signal but the 1v signal only reaches about 0.8v (regardless of the value of the 50 ohm resistor). I suspect that this is due to the difference between Vs and Vg being insufficient to fully turn on the mosfet.

Initially I'd steered clear of PMOS devices because I was aiming for something like 4ns rise time. We've relaxed that to about 9 now so maybe a push-pull thing with one N and one P?

 The application is something complicated to do with counting photons that I don't fully understand. (A common situation as an electronics tech in a university physics dept!)

Cheers all.

[c4757p]

How about a voltage divider followed by a buffer? An emitter follower should do unless the output voltage is critical. Even basic transistors can run quite fast as unity gain buffers.

[jahonen]

Put beefier buffer after FPGA and divide output of that into 2V non-loaded so that the divider has 50 ohm output resistance (like 82 / 120 ohms). Or, if you believe that the matching in receive end is good enough, then you could just put a 120 ohm series resistor from 3.3 volt output and let the receiver termination take care of the reflections (it works if it is good enough). Of course, having both ends terminated is the best solution since all reflections will be attenuated on each end.

Regards,
Janne

[Rufus]

I have an FPGA with a 3.3v digital output which can supply at most a few mA. I need to interface this to a device which has a 0 to 1V input which is 50 ohm terminated.

What FPGA - sounds a bit wimpy.

[muvideo]

You could try to buffer the output with a tinylogic chip, and feed a
resistor divider. Parts like the NC7WZ family, should be capable
to less than 10nS risetime.

Fabio.

[DenzilPenberthy]

What FPGA - sounds a bit wimpy.

I can't remember exactly what it is, it's some National Instruments thing. Like a breakout board with loads of analogue and digital I/Os from a computer but with an FPGA in it so you can do some logic stuff before it goes into the computer.

I'm going to grab a few of these buffers and have a play.

http://uk.farnell.com/diodes-inc/74lvc1g17se-7/logic-schmitt-trig-buffer-sot353/dp/1893834

Plan 1, run buffer at 2.0v with resistor divider on input and 50R resistor on output

Plan 2, run buffer at 3.3v with 120R series resistor on the output

and see which works best. Plan 1 might be better for dealing with reflections but Plan 2 might be a bit faster running the buffer at a higher voltage?

Cheers for the help and I'll let you know how I got on.

[free_electron]

simple PNP transistor.
emittor to 1 volt
base via a 220 ohm resistor to fpga pin.
collector to the circuit you need to feed.

make FPGA pin high: transistor turns off : 0 volt at collector...
make fpga pin low : transistor turns on : 1 volt at collector.

easy no ?

[muvideo]

F_E nice solution, but wouldn't the pnp transistor risk saturation?
The out can be slow to return to 0, but maybe this is not a problem at all.

At this point how about buffering a resistor divider with an emitter
follower? A "light" resistor divider to 1.6V, driving the base of an npn,
collector to 3V3 and emitter to output.

[Rufus]

What FPGA - sounds a bit wimpy.

I can't remember exactly what it is, it's some National Instruments thing. Like a breakout board with loads of analogue and digital I/Os from a computer but with an FPGA in it so you can do some logic stuff before it goes into the computer.

The National RIO things appear to use Xilinx Spartans. Spartans have configurable drive strength up to 24mA driving within 0.4v of the rails - probably a bit stronger than the 74LVC buffer you were talking about. So the buffer is probably a waste of time (apart from giving a bit of protection to the Spartan on the NI board).

My guess is a Spartan output configured for LVCMOS33 and 24mA with 75R in series and 130R to ground will give you 1v out and a good 50 ohm match and termination. I think there is some IO bank total current limitation on the Spartans so you may need to be careful if you have a lot of them.

Or like jahonen said just around 110R in series if you think the far end match is good.

[free_electron]

F_E nice solution, but wouldn't the pnp transistor risk saturation?
The out can be slow to return to 0, but maybe this is not a problem at all.

At this point how about buffering a resistor divider with an emitter
follower? A "light" resistor divider to 1.6V, driving the base of an npn,
collector to 3V3 and emitter to output.

he claims he is drawing power from the 1 volt  so turning off the transistor the collector voltage will collapse very quickly.

there is one caveat though .. we are reverse polarizing the b-e junction ( fpga output high pulls base above emitter... ) you can do that but no more than 4 to 5 volt. after that you get irrepairable beta degradation. that stuff is destructive for transistors.

For those not in the know :

The base-emitter diode of a transistor is very small compared to the base collector part. Chemically they are also doped differently. the base-emitter diode cannot have large reverse voltages. most transistors are killed if they get more than 5 to 6 volts there in reverse ( the base collector can have hundreds, or thousands of volts in certian cases breakdown voltage )

If you go over the collector-base voltage limit the transistor will avalance uncontrollably and catastrophic failure happens.
not so with the base-emitter diode. if you get that thing to avalanche you will inject 'hot carriers' into the base. What happens is essentially charge gets trapped in the depletion layer. this charge makes the transistor 'leak'. the net effect is that its beta (hfe) goes down. this process is (almost) irreversable. You can recover partially by releaseing the 'hot carriers' by baking the transistors at high temperatures ( 200 to 300 degrees) for 24 or more hours. this lets the trapped charge leak away restoring the transistors operation.

[kxenos]

   Ehm, right. I was going to propose using a fast rail to rail op-amp like AD8063 but nevermind...

@free_electron: How old are you? I'm asking because I want to know if I stand a chance learning this stuff in the next 50 years or so! And where do they teach this stuff anyway!

[muvideo]

he claims he is drawing power from the 1 volt  so turning off the transistor the collector voltage will collapse very quickly.

there is one caveat though .. we are reverse polarizing the b-e junction ( fpga output high pulls base above emitter... ) you can do that but no more than 4 to 5 volt. after that you get irrepairable beta degradation. that stuff is destructive for transistors.

Yes, as you said, it shuld be safe up to about 5V, unless the transistor is some
fast one, if I remember correctly, some fast parts claim 3V abs. maximum for reverse b-e.

if you get that thing to avalanche you will inject 'hot carriers' into the base. What happens is essentially charge gets trapped in the depletion layer. this charge makes the transistor 'leak'. the net effect is that its beta (hfe) goes down. this process is (almost) irreversable. You can recover partially by releaseing the 'hot carriers' by baking the transistors at high temperatures ( 200 to 300 degrees) for 24 or more hours. this lets the trapped charge leak away restoring the transistors operation.

This makes me curious, repairing old equipment, sometimes I've found dead transistors
with very low beta.  The two junctions test good with the diode tester, but the beta
is too low. This could be the reason of what I found into the fluke 343a.
It's output is driven by 4 2N3739, the previous owner made a mistake trying to repair it,
messing the main voltage selector and the transistors were probably exposed to excessive
voltages.
The result is one open,  one still working, and two without gain. I wonder if they could be recovered... just for fun.

Fabio.

[NiHaoMike]

What about a RF NPN transistor acting as a buffer along with a series resistor?