Electronics > Projects, Designs, and Technical Stuff

Full Adder on a breadboard

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Renate:
If you'll excuse a little trip down the rabbit hole, you might find this interesting...

You can take a logic circuit and put an inverter on each of the inputs and each of the outputs.
It will do something now, but will it be the same?

Let's take a piece of wire (an "IS" gate) and put one inverter on the input and one inverter on the output.
Does it react the same still? Yup, it's an "IS" gate.
We can do this with an inverter too, making 3 inverters in a row, still an inverter.

If we take a NAND gate and put an inverter on each input and one on the output we actually get a NOR gate.
You can verify this for yourself.
https://en.wikipedia.org/wiki/De_Morgan%27s_laws

So, either inverting all inputs and outputs OR inverting the sense of what you are calling a "1" or "0" amounts to the same thing.

In the breadboarded circuit, Q1-Q4 form a half adder, that is a 2 input adder.
Normally you need a 3 input adder to deal with carries.
So we have Q1-Q4 cascaded into another half adder (Q5-Q8) to accept that incoming carry.

My problem/confusion/stupidity was thinking that a half adder couldn't live with inverters on input and output.
Since Q1 has to detect the carry (if Q1-Q4 were operating in isolation) then they had to be using negative logic, that is, Gnd is a "1".
Why? Because Q1 normally would be considered a NOR, but we need something in the AND family.

But! Since this is all part of a 3 input adder, it all comes out in the wash.
The breadboarded circuit is fine if you consider Gnd a "1" or if you consider Vcc a "1" or if you invert all inputs and outputs!

Let's look at some adders, starting with a 1 input adder.
A 1 input adder??? Sure it follows the rules of all adders, it counts ones.
We fill out the truth table, then we change all 1's to 0's, then we put it in order and see if it's the same as the original.

--- Code: ---       inv        rev
 A  X       A  X       A  X
 0  0  -->  1  1  -->  0  0  GOOD!
 1  1       0  0       1  1
--- End code ---
So that works!

What about a 0 input adder? It counts ones. Obviously, there are zero of them.

--- Code: ---    inv     rev
 X       X       X
 0  -->  1  -->  1  BAD!
--- End code ---
Ok, now we're at the half adder, a 2 input adder.

--- Code: ---             inv              rev
 A  B  X  Y       A  B  X  Y       A  B  X  Y
 0  0  0  0       1  1  1  1       0  0  0  1
 0  1  0  1  -->  1  0  1  0  -->  0  1  1  0  BAD!
 1  0  0  1       0  1  1  0       1  0  1  0
 1  1  1  0       0  0  0  1       1  1  1  1
--- End code ---
Well, what about a 3 input adder (like the breadboard)?

--- Code: ---                inv                 rev
 A  B  C  X  Y       A  B  C  X  Y       A  B  C  X  Y
 0  0  0  0  0       1  1  1  1  1       0  0  0  0  0
 0  0  1  0  1       1  1  0  1  0       0  0  1  0  1
 0  1  0  0  1       1  0  1  1  0       0  1  0  0  1
 0  1  1  1  0  -->  1  0  0  0  1  -->  0  1  1  1  0  GOOD!
 1  0  0  0  1       0  1  1  1  0       1  0  0  0  1
 1  0  1  1  0       0  1  0  0  1       1  0  1  1  0
 1  1  0  1  0       0  0  1  0  1       1  1  0  1  0
 1  1  1  1  1       0  0  0  0  0       1  1  1  1  1
--- End code ---
And since you've gotten all the way down here, I can tell you that the next adder that works with DeMorganizing is the 7 input adder. ;D

ziptol:
This is really interesting, thanks!
Admittedly, after getting shaky results from making an adder out of AND gates and OR gates, I was looking online and found that you could make an adder out of both NAND and NOR gates. I picked the NOR adder because it would take fewer transistors and in my haste to get an adder on a breadboard, I neglected to actually find out why both worked and left it up to some logic wizardry. Working through how these things is the whole reason I took up this project, so this is super helpful for me!

LeoTech:

--- Quote from: Renate on December 10, 2019, 01:25:14 am ---
--- Quote from: LeoTech on December 09, 2019, 03:59:05 pm ---Then you need tri-state buffers...
--- End quote ---
I think that I'd just use open collector buses, it's much easier.

--- End quote ---

That seems like a far better solution, indeed. Although I have to admit, that I do not know to much about it.


--- Quote from: ziptol on December 09, 2019, 08:48:17 pm ---Let me know what you think! Is there anything that I might be missing/overlooking/getting wrong in my design?

--- End quote ---

Your design will undoubtedly work, but I might use an architecture along the lines of:


This will save you quite some Logic Gates, as you do not need as many control signals and the accompanying logic.
Besides that, it will also save you one clock cycle for each add machine cycle. (May depend on the rest of the architecture, but it will not increase the number of clock cycles at least.)

The way it works, is that you load one of the numbers you want to add into the B register from the input - which I just realized, I forgot to draw - after that the second number will be present on the wBus, aka the input register will be enabled. The ALU then automatically add these two numbers together, and if you set the write signal for the A register high, then the result will be stored in there. After that the output of A reg can be enabled and the write signal for the output register will be high.

I sincerely hope, that this explanation makes sense. It can be summarized as:

--- Code: ---0:
Enable input, Write B,
1:
Enable input, Write A, //Remember to enter a new number into the input for this step, if you wish to add something else than the same number twice
2:
Enable A, Write Output

--- End code ---

Btw, your post has inspired me to try and create a 4 bit CPU architecture for an FPGA based CPU myself, thank you ;)


(Sorry for the delayed response, I have been traveling.)

ziptol:
Update:

I received my shipment of parts from DigiKey yesterday and put together the rest of the full adder. I removed the test connections from the adders so the whole thing would be easy to see, but it's been tested and works perfectly!



Next up is the registers. I've designed some D Flip Flops, but it's a total of 7 transistors per Flip Flop plus 2 transistors for the activation, so if anyone has any suggestions for how to make it more efficiently, that would be much appreciated.



intabits:
Have you considered DTL rather than RTL?
I've always thought that the former was supposed to be be superior, though I can't justify that statement just of the top of my head right now.
(No more complex than RTL? Better logic level integrity?)

Seven transistors for a flop-flop does seem excessive to me, I always thought 2 or 4 would cover most use cases.
See P27 of:-
http://bitsavers.org/pdf/ibm/logic/223-2618_DDTL_Component_Circuits_CEMI_Sep1963.pdf
(IBM called flip-flops "triggers")

Some more good reads from IBM:-
http://bitsavers.org/pdf/ibm/logic/Walsh_-_IBM_Current_Mode_Transistor_Logical_Circuits_1958.pdf

Early stuff (vaccum tubes), but still valid principles:-
http://bitsavers.org/pdf/ibm/logic/223-6746-1_700_Series_Data_Processing_Systems_Component_Circuits_Apr1959.pdf

Standard Modular System (SMS) - I have hundreds of these, maybe I'll try something simlar one day...
http://ibm-1401.info/IBM-StandardModularSystem-Neff7.pdf

How they are used to make a computer:-
http://www.bitsavers.org/pdf/ibm/1620/fe/227-5751-1_1620_Model_1_Customer_Engineering_Manual_of_Instruction_Aug63.pdf

My very old SMS card page:-
http://members.optushome.com.au/intaretro/SMSCards.htm

And others:-
https://hackaday.io/project/8449-hackaday-ttlers/log/130460-bizarre-dtl-logic-levels-the-discrete-component-pdp-8
https://bootlicker.party/posts/ibm-sms-logic/

IBM used odd terminology, and weird voltage levels (compared to +5v). The above manuals were for internal use, so a fairly heavy proprietary slant, but still interesting and informative.

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