Clock gate circuit architecture

[promach]

For https://www.design-reuse.com/articles/34973/low-power-high-density-clock-gate.html ,  could anyone explain how the following newly proposed clock gate circuit architecture works ?

1. How does it reduces the clock-to-out path by merging the internal latch sequential loop and clock invertors ?
2. How does it saves an area of equivalent to 2 inverters ?