Generating a clean, narrow, high voltage, high current pulse for inductive load

[bonelli]

Hello,

For some scientific stuff, I have to build a high voltage pulse generator (from hundreds of volts to kV), able to generate very quick pulse (5-20ns) into small a small inductive load (estimated between 15 and 300nH).

The architecture is based on a flyback boost converter charging a bank of ceramic capacitors. A very fast MOS triggered by an external trigger closes the circuit, discharging the capacitors into the load. I have already build some (dirty) prototypes using Si-MOS. I'm now looking for a GaN MOS.

I'm concentrating on the block driver+MOS+cap+load. As a first step, I'm simulating the ideal circuit, omitting parasitic trace inductance.

I have a strange behavior on the drain : depending of the voltage of the capacitors bank, it may - or not - clamp the drain to the source (and therefore, the ground).



Simulation, 50V : output pulse is ok


Simulation, 200V : output pulse is narrowed and Vd low level is not ground.


Simulation, 500V : output pulse is narrower, strange step effect. Carefully look at Vd low level : it never goes to 0.


Simulation, 200V, 3 MOS in // : output pulse is ok


When replacing the L by a R, the output pulse is good. I thinking to a L/Coss resonance effect or something like that. I'm not sure to understand the phenomena, and so not able to resolve it.

I have tested a quite different MOS from the same brand, result is quite the same.

If a analog guru read this, feel free to any advice
Thanks !
 

[Conrad Hoffman]

Well, fundamentally you can't change the current in an inductor as a step function. Everything else probably stems from that.

[magic]

Random guess: is your gate voltage enough to support so much current in the FET?
It looks like it only starts to turn on near 5V and works until current exceeds 20A per transistor, then the weird stuff appears.
You can also see some RDS(on) on the first trace.

[silverback]

All looks exactly like it would be. What you have forgot is the gate drain capacitance. When you turn on the FET the drain voltage falls and try's to turn of the FET by lowering the gate voltage. The opposite occurs when you turn off the FET, the drain voltage rises. This causes the gate voltage to be pulled up keeping the FET ON. This can be really seen with the high voltage supply, you can see the FET being turn on again. The oscillations you see is when the gate drain feedback capacitance causes the FET to be in its linear region. Should you be looking at generating the higher voltage when you turn off the FET? Change D1.     

[mawyatt]

What you are seeing is called the "Miller Effect", for a MOS type (any type) the charge in the gate must be supplied to completely turn ON the FET, and likewise must be removed to turn OFF the FET. As mentioned in-between ON and OFF is the linear region where sporadic oscillations are common. A stronger gate driver will help subdue these oscillatory effects.

Best,

[bonelli]

Well, fundamentally you can't change the current in an inductor as a step function. Everything else probably stems from that.

Actually, a linear di/dt ramp is good for my application. I'm looking to maximize di/dt, and driving the inductor with a square voltage, di/dt=U/L so I'm looking for high U.

[bonelli]

Random guess: is your gate voltage enough to support so much current in the FET?
It looks like it only starts to turn on near 5V and works until current exceeds 20A per transistor, then the weird stuff appears.
You can also see some RDS(on) on the first trace.

Maybe not. I started the design with GaN transistors from EPC, that works fine with 5V gate drive (6V absolute max). But EPC max Vds is "only" 200V, this is to much limiting for my design. So I tried with TP65H150G4LSG that support Vds=650V, omitting to update the drive circuit.

I have just tried to drive directly the gate by a 10V voltage source (with HV=500V) :

This is quite better since Vd really goes down to 0V (I don't care about a few volts caused by Rds(on)). But I still have the miller plateau effect and don't see how I can drive the gate more "hardly"

[Le_Bassiste]

have a look here:
https://www.behlke.com/

[T3sl4co1l]

Don't worry about turn-off, just leave it on.  Dimension the pulse network to do whatever it needs to do from that one edge.  This sounds like a EFT (electrical fast transients) waveform, give or take exact shape.  GaN isn't necessary here, you'll need either a stack of them (cascode) to get the voltage, or a lot in parallel with pulse transformers to match it up.  SiC has higher voltage rating, and adequate speed.  Even Si has adequate speed, just barely, but you'll definitely need to use them in parallel with matching transformers.

Transformers are annoying, for such voltages and power levels, but transmission line transformers aren't too bad as far as ease of construction and signal quality.  Getting adequate gate drive in a cascode stack, and syncing them all to turn on not just at the same time but the same rate as well, is not trivial.  On the upside, that'll be easier to do with the low Qg of GaN; on the downside, you have a very narrow voltage window in which to drive the gate, and that's not an easy target to hit when you're doing several kV alongside it.

Tim

[bonelli]

you'll need either a stack of them (cascode) to get the voltage, or a lot in parallel with pulse transformers to match it up.

Are you talking about gate drive transformers?
https://www.coilcraft.com/en-us/edu/series/a-guide-to-gate-drive-transformers/
The TP65H150G4LSG used in my simulation is internally in cascode mode.
Using 2 in parallel, with 10V gate drive, did solve the problem. I should now work on the driving circuit and simulate all this stuff adding parasitic stray inductors to see if things are still good.
Why should I use pulse transformers to drive the gates, instead of simply drive them in parallel, since the MOS sources are ground-referenced ?

I was thinking about using one driver per gate, or paralleling drivers, connecting all drivers outputs together to drive all gates. For layout reasons the first one may be more easy to route.

[mawyatt]

Use a Cascode to reduce the "Miller Effect", this works by forcing the "Gain" as seen from the input to ~ unity, thus reducing the effect. A very effective type of GaN and Silicon Bipolar or MOS combination is to utilize a depletion mode GaN device and a Si bipolar transistor or MOS. The input now is the Si bipolar or MOS device and the output is the GaN Drain, very fast and high power/voltage capable 3 terminal device. See patents 7939857 & 7903016 where we coined the term GaNsistor (1st patent) and DD2A (Direct Digital to Antenna, 2nd). These are very effective at creating fast, high power, arbitrary RF/MW/MMW waveforms. A fast high power Traveling Wave DAC was created utilizing multiple DD2As in a DARPA program called Power DAC.

Best,

[jonpaul]

Bonjour cher Monsieur je suis ingénieur spécialiste haute voltage et magnétique pulse.

Si vous êtes en la France, je peux assister.

Je Arriverait à Paris plus tôt, donc nous pouvons appeler ou RDV.

svp Me contacter avec message privé

Bon week-end
Jon

[mawyatt]

What you are seeing is called the "Miller Effect", for a MOS type (any type) the charge in the gate must be supplied to completely turn ON the FET, and likewise must be removed to turn OFF the FET. As mentioned in-between ON and OFF is the linear region where sporadic oscillations are common. A stronger gate driver will help subdue these oscillatory effects.

Best,

Made a quick sketch to show these concepts so folks don't have to suffer thru the patents. Remember the first implementation while waiting for a test chip in IBM SiGe BiCMOS 9hp and didn't have any discrete fast transistors laying around. Did have a new Raytheon GaN device, so grabbed a bunch of 2N3904s and kludged together a simple Current Mode Amplifier. Recall the results were quite good indeed

Best,

[magic]

TP65H150G4LSG is already a MOSFET-JFET cascode
Besides, this doesn't look like typical Miller problem: drain voltage falls cleanly and weirdness begins later.

I wonder if the model you are using includes some package inductance which causes ringing on the internal gate voltage (that you don't see).

BTW, what's the way to peek at the action inside a SPICE subcircuit?

[mawyatt]

TP65H150G4LSG is already a MOSFET-JFET cascode

Yes it is a GaN Depletion mode FET with MOSFET, and a flagrant patent infringement, as are a number of other suppliers 

Awhile back we notified the present patent owners legal counsel regarding these infringements, they decided not to pursue because of long term gains since infringement cases last many years and they were looking for short term gains because they were in the process of being acquired/merging. Even thought about purchasing the patents and filing multiple infringement cases, but that would be an expensive long term "investment" and not our style!!

Edit: This would be a classic place for a patent troll to acquire the patents and litigate even tho they had/have nothing to do with the use, development and creating of the IP!!

BTW the gate voltage plateaus are classic Miller Effect caused where the gate charge must either be removed or supplied by the driver.

Best,

[T3sl4co1l]

you'll need either a stack of them (cascode) to get the voltage, or a lot in parallel with pulse transformers to match it up.

Are you talking about gate drive transformers?
https://www.coilcraft.com/en-us/edu/series/a-guide-to-gate-drive-transformers/
The TP65H150G4LSG used in my simulation is internally in cascode mode.

I mean like, this is an example:
https://indico.cern.ch/event/677656/papers/2930394/files/7758-An_8kV_Series-Connected_MOSFETs_Module_that_Requires_One_Single_Gate_Driver.pdf
from the OG physics pulsers no less, CERN.  The gate drive capacitors might be in a divider alongside the stack instead, or with GDT windings, but you need some way (probably Miller capacitance) to synchronize the gate voltages, otherwise a few turn on first (or faster than the others), MASSIVELY increasing the voltage on the remaining parts.  I'm not sure offhand how SiC fares with avalanche, but GaN simply explodes at the slightest touch.

It looks like several papers discuss calibrating gate drives.  One by adjusting timing on an auxiliary drive MOSFET, one by tuning D-G feedback, one (above) by tuning C(G-GND), etc.  I suppose that works in the physics lab.  Maybe it'll work here too, no idea.

Tim

[mawyatt]

TP65H150G4LSG is already a MOSFET-JFET cascode

Thanks for identifying this potential infringement, proper legal counsel has been notified and will decide if they want to pursue 

Best, 

[magic]

Not quite sure which claim of the two patents you have posted is supposed to be infringed upon.

Anyway, have fun suing them for a circuit idea which appears in The Art of Electronics

[mawyatt]

Not quite sure which claim of the two patents you have posted is supposed to be infringed upon.

Anyway, have fun suing them for a circuit idea which appears in The Art of Electronics

For one, it's the GaN integration with the Silicon MOS, although likely other cases as well.

Couldn't find this in the book you mentioned (please post page/diagrams?), nor anywhere else could we find anything during the prior art searches long ago which included multiple expert patent attorneys, even with one of the worlds leading authorities on GaN technology (late Dr. Robert Trew, we approached him as a consultant), and the orginial discovery dates back to ~2004. 

Even DARPA created a program in 2011 centered around this GaN Si technology, called Power DAC (see patent 7903016)

https://www.militaryaerospace.com/defense-executive/article/16716367/darpa-to-integrate-da-converters-and-amplifiers-to-enhance-power-efficiency-for-ew-sensors-and-communications

So if you have "claimed" information on prior art, or maybe some published or unpublished pages from Dr. Horowitz's books, or anything that predates the discovery around ~2004 please show us your "claimed" findings!!

Here's some reading for additional education/enlightenment on the subject just for fun, note the dates on the references

https://www.sciencedirect.com/science/article/pii/S2667325821002867

Even predated International Rectrifier efforts discussed here:

https://eepower.com/technical-articles/power-conversion-with-gan-on-si-integrated-circuits/#

Also looked into an integrated Si Depletion Mode MOS device with the Enhancement Mode MOS (sorta like old DMOS logic) way back, but discounted this since it was slow and would severely limit the speed.

BTW, we don't "own" the patents they are assigned and the owners decide on how to proceed, we just alerted them to your finding

Best,

[Marco]

and the orginial discovery dates back to ~2004. 

Doesn't really matter for prior art, even under first to invent.

A GaN JFET cascode is going to be ruled an obvious variation on SiC JFET cascodes if it ever turns into a real fight, they are used for almost the exact same reasons. SiC JFET cascode prior art is way older than the filing date of 7939857.

[magic]

The Art of Electronics contains multiple examples of JFET cascodes. There are of course other examples elsewhere, and examples of depletion MOSFET cascodes too. If you think that using a particular type of JFET is innovative enough to justify a patent in the 21st century, have fun fighting such case in court (or having somebody else do it). That's all I said.

But you don't even believe it yourself. Neither of the patents you mentioned attempts to claim the use of any sort of cascode over a single transistor, which is exactly the kind of product we are discussing here. It's entirely out of the scope of your patents, as you wrote them.

 

[jonpaul]

Rebonjour Cher Myawatt,

About your discussion about FET GAS GAN patents, a moment please!!!

I have long experience in patents, both procecution, enforcement, liscencing and litigation since 1977, (160 lawsuits and settlements, over a 15 years period).

First patent searching, litigation and enforcement is a long and complex discussion.

Nowadays it takes  5....15 years and 1..5 M$ legal expense to bring a single case.( not to win!)

Especially since the American Invents law of 2017, Patent law and litigation in USA greatly disadvantages the small entity inventor vis à vis the large firms.

Notice that a valid search must encompass all patents worldwide, all languages and is not limited to US patents, as any publication, paper, etc can serve as prior art.

Bon courage

Jon

[Terry Bites]

This could be BS. If you create a negative inductance (which is possible) to drive your inductor then if they are equal the net indcutance is zero and the current will see a resistive circuit.
Madness.