Looking at a copy of Zilog's data sheet UM008011-0816, figure 10, I don't see /M1 and /IORQ asserted simultaneously for an NMI response.
I agree with the previous post that there are likely more errors in the schematic. If Q1C had its collector and emitter swapped it would be trying to pull /NMI high hence the inclusion of R6 to limit current and act as a load resistor. When /M1 is asserted and then negated, it might vary the voltage on /NMI enough to be detected as a transistion - but I think it would be iffy given these values. I could think of better ways to do this with more conventional designs.
BTW, Q1C could be operating in reverse mode where the collector and emitter are swapped. In this mode it will have a very low hFE and Vcesat. I can't think of an advantage here so I suspect it's a typo.