Timing constraints should be considered quite early on design, although it seems that 100 MHz should be easy, there can easily be quite slim window of success, when you add all the timing budget things together. For example, bad selection of FPGA pins may lead to non-achievable timing target, be careful with that.
Signal integrity simulations are also useful. I can only give advice that use point-to-point wiring wherever possible, multidrop bus is considerably more difficult to design, and may be even impossible if IO-pin drivers are not hefty enough. You can easily get very strange and extremely difficult to find faults if your signal edges are not monotonic enough (been there, done that!). Again, the signal integrity simulator will show a good estimate if your driver is up to task.
Dynamic RAM needs refresh cycles now and then (I believe that in intervals of ~8 µs), furthermore there is a maximum time that a page can be open at one time. Result is that data rate is somewhat lower than one would expect. Synchronous static RAM is able to sustain new data on each clock period, but that is several orders of magnitude more expensive. For best latency and difficulties, the acquisition clock frequency should be designed in such way that there is no need for clock domain crossing logic, that can be a pain sometimes. Although FPGAs usually feature a dual-clock FIFO, which solves the problem.
Regards,
Janne