Digital Oscilloscope

[Sebeom]

Hello,

I  have a plan to design a digital oscilloscope. The ADC sampling rate is 5GSPS. We will get the ADC data using FPGA. We need higher sampling rate for high-end oscilloscope. So we consider the ETS(Equivalent Time Sampling). In case of random ETS, we need to know the time of ADC clock rising edge after trigger event using TDC(Time to Digital Converter). I think this job is very challenging because TDC time resolution need to be around 10ps. Is there anyone who has a good idea to implement the higher sampling rate using the other method?

Thanks, Sebeom

[marshallh]

You will want to use digital triggering then. Good luck, what you described is non trivial.

[Sebeom]

You will want to use digital triggering then. Good luck, what you described is non trivial.

If I use the digital trigger, there will be the the way to increase the sampling rate without ETS. Is it possible? If so, Could you give me some technical information how to implement the digital trigger to the system?

[Lukas]

Digital trigger is basically equivalent to a transition midpoint timing TDC. You look at the sample before and after the trigger level, connect them linearily and determine the time at which the line intersects with the trigger level. If you get more fancy, you can use more samples and to sin x/x interpolation to pinpoint the trigger event.

A while back I did some simulations and experiments on a dual-slope TDC with an interpolation factor, unfortunately I haven't been able to characterize it regarding linearity and noise.

[Sebeom]

Digital trigger is basically equivalent to a transition midpoint timing TDC. You look at the sample before and after the trigger level, connect them linearily and determine the time at which the line intersects with the trigger level. If you get more fancy, you can use more samples and to sin x/x interpolation to pinpoint the trigger event.

A while back I did some simulations and experiments on a dual-slope TDC with an interpolation factor, unfortunately I haven't been able to characterize it regarding linearity and noise.

Do you means that although I use the digital trigger, I need to implement the TDC to know the time information before or after the trigger level?

[Lukas]

When using digital trigger, the ADC in the scope in conjunction with the band-limiting of the analog frontend, you get a TDC for free, no need for external circuitry.

An external TDC is needed for equivalent time sampling.

[nctnico]

Hello,

I  have a plan to design a digital oscilloscope. The ADC sampling rate is 5GSPS. We will get the ADC data using FPGA. We need higher sampling rate for high-end oscilloscope. So we consider the ETS(Equivalent Time Sampling). In case of random ETS, we need to know the time of ADC clock rising edge after trigger event using TDC(Time to Digital Converter). I think this job is very challenging because TDC time resolution need to be around 10ps. Is there anyone who has a good idea to implement the higher sampling rate using the other method?

Thanks, Sebeom

What kind of bandwidth do you aim for? And why don't you buy an off-the-shelve solution? I think that will be cheaper than building it yourself unless you have very specific requirements.

[ez24]

We need higher sampling rate for high-end oscilloscope.

What will be your retail price?  I do not know of any Korean scopes, are there any being made in Korea?  Don't forget documentation.

[nctnico]

We need higher sampling rate for high-end oscilloscope.

What will be your retail price?  I do not know of any Korean scopes, are there any being made in Korea?  Don't forget documentation.

They better start with writing the software if they want to create a commercial product. That is a vastly more daunting task than sticking some fast ADCs on a board.