GND pour beneath power inductor (choke)

[Ashwin619]

Hello all,

I am designing a small Buck converter which has a switcher IC with integrated FET. While designing the PCB layout, I have come across an option to either keep the GND pour beneath the choke (top layer) for a better return path OR else remove it to avoid any eddy current generation due to the leaked flux coupling with the GND plane.

There's an article by Zach Peterson from Altium where he has concluded that having a GND plane below the inductor (considering its fully shielded) would be a better option than not placing it.
Link- https://resources.altium.com/p/should-ground-be-placed-below-inductors-switching-regulators

A similar much detailed article by Kenneth Wyatt also gives a kind of similar conclusion from the EMI perspective (although they have considered the cutout in the bottom plane and not the top one)
Link- https://www.signalintegrityjournal.com/blogs/17-practical-emc/post/2694-dc-dc-converters-solid-return-plane-or-cutouts-under-switch-node-and-inductor

I am using a fully shielded inductor and I believe using a GND plane (in my case) beneath the inductor (top layer) would be better option considering the return path it provides from the O/P caps GND to the IC GND (pin 5).

I would really appreciate if someone could shed some more light on this topic and perhaps also share their personal experience.

Image of the layout-


 




 

[Psi]

A lower inductance / higher current path is preferable.
Since you want your switchmode loop as tight as possible.

So yes, use as much fill as you can.

[T3sl4co1l]

Well, switching loop is between regulator and diode, doesn't matter as much under the inductor, just to clarify.

But not to say the loop doesn't matter here.  Shorter and... erm, poured-ier, is still better.

The main reasons you'd avoid pouring under an inductor are if it has significant external field and you need to keep its Q high (copper resistance would load down the Q), or if those external fields are exactly the point (e.g. making a tuned network, coupling between adjacent inductors; see also RFID, wireless charging, radio antennas..).  And in those cases, just top side copper won't be the most important, but you'd need to make a hole through much of the board, and also avoid placing components near that hole, traces across it... But none of those reasons apply here, so yep.

Oh, you might remove top copper in the case that more insulation is required, say for an inductor that's got 500VDC on it that's only rated for 250V or something.  In that case, copper pour/plane on the nearest inner layer (and below) is still fine (or not, as determined by both the above reasons).

Tim

[Ashwin619]

Hey Psi,

Yes, I agree with your point that a better return path would be more beneficial than a slight decrease in inductance due eddy currents. Ill be sticking with the GND pour for now.

[Ashwin619]

Hi Tim,

Thanks for the great insights, as always. I surely agree that in a Buck the noisiest loop would be the one that has the switching FET and the diode (i.e. switching node) due to the discontinuous current from the FET as opposed to the continuous current loop containing the choke and O/P caps.

Insulation (clearance ?) should not be an issue in this case as the O/P voltage is 12V max.