Hmmmm, good point. There is definitely a risk here.
I would argue that I can prevent the transistors from exploding. But it would be at a significant performance limit. Assuming that all inductors are actually at their -20% limit, I can configure my maximum on time to ensure their current can't rise above a safe value (say 50A). Yes, this means that if the inductor is actually at +20% tolerance, then I'm running nowhere near peak power throughput for the power components, but at the same time, it does mean nothing will go bang (in normal operation).
The mismatch is a bigger worry and I may end up with 1 of the 4 phases doing 50% of the conversion, but again, providing my timing is such that I'm not exceeding SOA for each device, I don't see it as a magic smoke risk.
Of cause, this is all my opinion as an engineer very new to high power, high speed switching.... So, please keep punching holes

Plus, if I up my input voltage to 24v at half the current, then the performance degradation of playing it safe should be offset.
Way to do efficient, low cost, design

(sarcasm)
On the bright side, I think I finally grasped the physics of gate ringing last night and how the parasitics come in to play, why snubbers work, and why slowing the gate reduces the effect. So, as a learning exercise, this is working
