GPIO output noisy despite being driven to low

[zphaze]

Hi,

I'm driving a simple GPIO output on MCU. The GPIO output acts as a chip select (CS, manually driven) pin for communicating by SPI to a small DAC chip.
My issue is that the output of said GPIO/CS pin is unstable when driven to low, which corrupts SPI communications, as seen by the following logic analyzer screenshot :



Of course, it's not something I can get a definitive answer here, but I'm looking to some advices about what I should do.
Could perhaps having a pull-up, a 22ohm terminal resistor, a small bypass capacitor say ~500pF on the line could be a solution?

It isn't my design, I only picked it up from someone else (the PCB I mean). One thing I noticed straight off is that the SPI lines are connected end-to-end (MCU to DAC & other chips) without any resistors/pull-ups.
And the traces are somewhat long (well, around 10-12cm).

 It is a ATSAME70Q21B MCU. The MCU is on a Netburner MODM7AE70-200IR system on module card (for what it's worth), which is connected to the main board by 2x50pin headers.
I also have ADCs.

I initially saw this problem on ADCs, but to a lesser extent. What was weird with the ADCs is that the CS line would be fluctuating A LOT (like, a LOT) on 12MHz SCLK frequency, but when using 8MHz I was okay. 15MHz I had some here and there, 10MHz same, but 12MHz was really the worst. On 8MHz nothing happened.
On the DAC lines, it's different. I get them no matter what SCLK frequency I use. Some might be worse, but not as noticeable.

I wonder if I'm picking up noise. I used small wires soldered to VIAs to connect my logic analyzer, which could act as antennas. But I'm skeptical those are the issue.

Observing the picture, it seems like the CS fluctuations happen right on SCLK edges as well. Note that 3 bytes are sent on the line, during which CS is low, then CS is driven high again. No fluctuations occur when CS is high.

I'm looking for general advices on what to test or potential fixes/causes to have a better idea of what to do.

[ataradov]

You really need a scope for this. Or at least set the CS low for a long time and measure the voltage with a multimeter. It is possible that some levels are conflicting and you are not really getting a low level, but something at the edge of the LA threshold.

Also, did you connect the ground of the LA to the board ground?

[zphaze]

Hi Alex, yes the logic analyzer ground is connected to the board ground. Well, more specifically, the board is connected to a keysight lab power source, to which the logic analyzer is connected to as well, using banana cables.
Observing CS low for awhile with an oscilloscope sounds like a good plan for the next steps, indeed. Thanks

I doubt the logic analyzer sees something wrong or causes this. As said, I tested before with ADCs as well, and at 12MHz I also saw what I see with the DAC CS line.
Upon disconnecting the logic analyzer completely, sampling a sine wave coming from a signal generator (with the said ADCs), and dumping the MCU ADC buffer to my computer without any instrumentation connected to those lines, I could see the SPI corruption on the sine wave inside that buffer using the JTAG debugger.

Ofc my current problem is more with the DAC lines and might differ from the ADC lines, but since it's the same symptoms (fluctuating CS), it's probably linked.

[ataradov]

Get a good ground connection. A mess of wires is not going to be helping the investigation. A scope will tell what is going on.

What pin you are using for CS? Do you have a schematic for that board? Are you sure there is not anything conflicting there?

E70 will have no issues driving the line low without any external filtering, so this is some system-level issue.