Battery prototype with balancing and monitoring

[DrMag]

This is a "learn by doing" project for me; I want to build an avionics module for inclusion in a model rocket ultimately to get a high-powered rocketry certification. Step one is the battery.

The intent is to build a prototype that lets me fully characterize and understand how the power system works, so I've added a battery balancing mechanism (capacitor shuttle) and cell voltage monitoring (buffered differential amplifier to ADC). Since the differential amplifier could, assuming something went terribly wrong, float all the way to the stack voltage (nominal 14.8 V), I added a simple zener protection on each ADC input.

Would love any feedback, so please poke holes in my design if you can!

[penfold]

Are those diff amps the right way round to produce a positive output?

With the 4052 powered from 3.3V, is the +BATT within the allowed range of input voltages? I scanned the datasheet and got the impression the inputs would be limited to about 3.3V... may have misread it thought?

[DrMag]

Both good questions -- based on https://www.electronics-tutorials.ws/opamp/opamp_5.html, I think I do have the op-amps oriented correctly.

As for the 4052 question, the wiring only has the capacitor across an individual cell at a time -- so at most 3.7 V. Based on the datasheet, it should be good to Vdd + 0.5 V. That's one of my biggest questions, though. Could be mitigated by not permitting balancing at full charge, but it's not as effective if that's the case. I suppose I could switch to a 5V micro... I just like using MSPs.

[DrMag]

... I take it back -- those op amps are backwards.   

Amazing how you can look at something dozens of times and still miss the obvious.   

[penfold]

based on https://www.electronics-tutorials.ws/opamp/opamp_5.html, I think I do have the op-amps oriented correctly.

They are configured correctly as differential, but to my eye they are subtracting a larger voltage from a smaller voltage resulting in a negative (EDIT.. I see you noticed)

As for the 4052 question, the wiring only has the capacitor across an individual cell at a time -- so at most 3.7 V. Based on the datasheet, it should be good to Vdd + 0.5 V. That's one of my biggest questions, though.

Section 9.2.2 of the datasheet says "Inputs should not be pushed more than 0.5 V above VDD or below VEE."
I believe this is absolute and not relative, likely due to protection diodes on the inputs which will be forward biased when the pin voltage exceeds the supply, so pin 11 for instance sees the full VBAT but the IC's Vdd is only 3.3V. There isn't a lot you can do to solve that problem apart from powering the 4052 off Vbat directly and buffering the control signals - since there's only three inputs it wouldn't be much extra to use logic level threshold MOSFETs to do the level shifting.

Also noticed that the TLV2252 is only rated to a Vdd of 8V, the 16V figure in the datasheet is an absolute maximum rating... and the input common mode range is only up to Vdd - 1.3V which means even if Vbat was a suitable supply voltage, the input to U4A would exceed Vdd - 1.3V. Is there any reason you need the buffer stage?
 

[DrMag]

Hm. I'd better look at that amplifier again. I like that it has a really high input impedance, which lets me get away with larger feedback resistors and reduce the power needed to run the whole thing.

The buffer stage is there because without it, the differentials would load the individual cells differently -- Cell 1 would be providing current to all four amplifiers, while Cell 4 would only be providing it to the fourth amplifier. That drives the cells out of balance. With the buffers, the amplifiers should load the battery evenly.

[penfold]

The buffer stage is there because without it, the differentials would load the individual cells differently -- Cell 1 would be providing current to all four amplifiers, while Cell 4 would only be providing it to the fourth amplifier. That drives the cells out of balance. With the buffers, the amplifiers should load the battery evenly.

You could forgo just the top buffer in that case, then its one less requirement to meet and even when spec'd to do so, running the inputs and outputs slammed up against the supply rail isn't always good.

[DrMag]

Ok, Rev B.

I updated the op-amp choice to one I think would serve well for this. Also changed for 4x dual-amps to 2x quad-amps.

Additionally, I set the CD4052B to Vbatt instead of 3V3 and added a CD40109B for level shifting between the MSP and the muxer.

That led me to upgrade to a slightly larger micro so that I could control the enable pins on the level shifter. Now I've got a handful of free GPIOs ... added another LED indicator; what else could I do on this board?

[penfold]

That looks better,

Does pin 13 on the 40109 need to be pulled low or is it best left floating? (I'd personally leave it floating, but seeing as its permanently low probably doesn't matter)

[DrMag]

You know, I'm not sure. I was going off the guidance I'm used to, though I recognize that grounding all unused pins is more a rule of thumb for micros. I suspect it won't hurt in this case, and the extra ground trace is essentially free when the pcb is made anyway.

If you or anyone knows of a good reference that would argue why it's better to leave something like this floating, I'd love to know about it.