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GPSDO: PLL or MCU controlled?
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Illusionist:
Ha - that Lars design is using the method I was thinking of for sync'ing my PPS... but for the main OCXO control. I think... need to read it but it looks like that.
David Hess:

--- Quote from: Illusionist on July 26, 2019, 10:26:49 pm ---The NEO outputs a 10kHz signal for the PLL, which is basically the same as the JRMiller design but with faster, SMD logic.
--- End quote ---

That will of course work however beware that the time pulse outputs are only updated at the GPS navigation update rate:

The time pulses are generated on edges of an asynchronous clock; for pulse rates below 2 Hz, the exact phase of the TIMEPULSE output is reported before each pulse in the TIM-TP message.

So frequencies higher than the navigation update rate do not provide any extra information and the phase comparator output still needs to be filtered to a very low frequency.  Otherwise the DO is going to phase lock to the oscillator producing the time pulse outputs with GPS guided discontinuities.  At least that is how I read the documentation for the NEO-M8T and if this was not the case, then there would be no need to report the phase of the time pulse outputs.

Based on the 20 nanosecond specification, I assume the clock is 25 MHz.
Illusionist:
Yes, I understand about the 10kHz not being 'better' - just simpler on the PLL. I was just reading the manuals regarding the TIM-TP message, in case I can utilize it.

20ns - from my post about sync'ing the derived PPS? The main dsPIC clock is the 10MHz OCXO, with the dsPIC multiplying it up to 100MHz and an instruction cycle of 50 MIPS.

The dsPIC generates a 10MHz output of its own (PWM) which serves as the clock for the divide-by-1,000,000 PIC, which gives the derived PPS.

By having the dsPIC tweak the PWM phase by a clock cycle (100MHz=10ns) just once for a single period, I can move the derived PPS phase in 10ns steps.

The problem I have is measuring the difference in the first place. I'm trying to use the CTMU in the dsPIC but it simply isn't behaving at all and I can't figure out why. I've just posted another thread in the microcontroller forum about that. That's where the limit of 20ns is coming from, simply from measurement on the oscilloscope. That's as close as I can get the CTMU to measure, so as close as I can adjust the phase.

If I can get the CTMU to work as advertised, I can then use the Maxim delay line to bring the derived PPS as close as my measurement resolution allows.
David Hess:

--- Quote from: Illusionist on July 28, 2019, 12:04:00 am ---The problem I have is measuring the difference in the first place. I'm trying to use the CTMU in the dsPIC but it simply isn't behaving at all and I can't figure out why. I've just posted another thread in the microcontroller forum about that. That's where the limit of 20ns is coming from, simply from measurement on the oscilloscope. That's as close as I can get the CTMU to measure, so as close as I can adjust the phase.

If I can get the CTMU to work as advertised, I can then use the Maxim delay line to bring the derived PPS as close as my measurement resolution allows.
--- End quote ---

I responded in your other thread about the CTMU.
fourfathom:
Sorry if this is obvious, but given the low frequency of the VCXO loop filter, you aren't stuck with the DAC LSB resolution, or the 10ns timing of the 100MHz clock.  Just use numeric pseudo-noise or other high-frequency dithering to provide fractional average resolution.  The high-frequency noise component will be filtered out by the loop filter.  The Bresenham line-drawing technique is another way to provide a very filterable fractional output and can be used in both time-domain and amplitude-domain (DAC) applications.
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