Electronics > Projects, Designs, and Technical Stuff

GPSDO: PLL or MCU controlled?

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Illusionist:

--- Quote from: Johnny B Good on August 04, 2019, 01:47:09 pm --- I realise it's a bit of an imposition to spring such a "left field" question 'out of the blue' on you like this...

--- End quote ---

Not at all, it's all good. Not that I can be of much help with the matter unfortunately.

One of the few decent investments I made some years ago was a Weller soldering station (the basic analogue temperature control one) and a couple of irons; a WSP80 for general soldering and a WMP65 micro pencil for the fine pitch stuff. I might make a different choice now, but at the time there wasn't as much choice and the Weller does the job perfectly well. It just takes up a bit too much of my very limited desk space.

The bigger WSP80 gets far more use, especially now I've discovered drag soldering. A bit late to the party perhaps, but I'm glad I got there. I persevered for ages with a 0.1mm tip on the micro pencil, soldering 0.5mm pitch ICs a pin at a time under the microscope.

The one bit of advice I would give, given that most interesting things now are SMD, is to get an iron that you can buy a gull wing tip for. They go by other names too and have a concave dish in the tip which holds a tiny blob of solder. I watched a few videos on drag soldering, then gave it a go on some 28 pin TSSOPs. The videos made it look ridiculously easy, and to my amazement it actually was. The flux was critical; I got a bottle of RA flux from Farnell along with the tip. It works much better than my flux pen for this purpose:

https://uk.farnell.com/mg-chemicals/835-100ml/rosin-soldering-flux-bottle-125ml/dp/2903909

I must admit that ublox module was a pain to solder. Making the rest of the board went like a charm (even the 0603 parts that were small enough to carelessly inhale) but that module just sucked the heat right out of the iron before it could make a joint. By the end of it I had turned up the heat to about 330C, iirc, with the WSP80 and was just managing to get good joints made without feeling I was going to overcook it or leave a cold joint. That was before I got that bottle of good flux though, which I think would have made quite a difference in getting the copper to wet. Still, it survived.

Should you change your mind about giving it a go, give me a shout about those spare PCBs.

I've not had chance to do anything with the GPSDO today, other than plot and scheme. As much as I like the (relative) simplicity of a PLL, my original idea was to use an MCU controller. I need one for sync'ing my derived PPS anyway. Using basic frequency locking control of the OCXO on an MCU though isn't conducive to keeping that DPPS where it should be. It drifts, slowly but surely.

It's much easier to use phase locking on the OCXO than to try to keep the DPPS sync'd without it. So... I'm considering doing the phase locking in the MCU, either with a capacitor and ADC or one of those TI chips mentioned earlier in the thread... implementing what I now know is known as a TIC. Along with learning how to use the dsPIC for actual digital signal processing. I could even try pressing the CTMU (essentially a built-in TIC) on the dsPIC to the task, but it seems so unstable I don't know if it's worth the effort.

...and then I wonder if it's all worth the extra effort when I can already get the OCXO more accurate and stable than I'll likely ever need. But that's not the point, I guess.

It's good to have choices  :-DD

Theboel:
 Hi illusionist,
Good choice for TIC+MCU.
In lars thread there is a paper about what he has done and reason why he done it it's very worthy to read.
Especially about temperature control. If You put the whole GPSDO in a thermal isolated box and use his temp control You will have DOCXO and your also You can keep everything in stable environment.
If You like maybe You can also add more thing like kalman filter, sawtooth correction to Your GPSDO

Illusionist:
Theboel, yes, I've been reading about Kalman filtering. Trying to understand it, and how to implement it.

I do think that phase locking is the best way for what I'm trying to achieve and it would be fun (if a steep learning curve for me) to implement it in a MCU. While my current design works quite well, I like the further challenge.

I've glanced over Lars' design but don't want to read it in depth because I really want to figure it out myself. I'm trying to balance reading and learning enough to do it, and discovering others' ideas that might be helpful, without just duplicating their work.

As a hobbyist, all of this is just for fun and a learning exercise. It also lets me indulge my obsession for accuracy and precision.

edigi:

--- Quote from: fourfathom on August 03, 2019, 08:09:51 pm ---What kind of specs are you looking for here?  I'm surprised that you can't get these deterministic delays with a CPLD, since 100MHz (and faster) internal clocking is pretty typical and with clocked outputs the delay variation will be within a couple of nanoseconds.

--- End quote ---

What I actually wrote that with CPLD you do get more deterministic delay than with FPGA (unless CPLD is internally uses an FPGA like architecture). No other clock is involved in my solution than the 10 MHz (the reference that is GPS disciplined) and the GPS pulse output.

Sure, that the biggest noise contributing factor is the jitter from the GPS pulse output (https://www.u-blox.com/sites/default/files/products/documents/Timing_AppNote_%28GPS.G6-X-11007%29.pdf), however it costs close to nothing to practically entirely eliminate the uncertainty of the GPS pulse period measurement in reference periods terms (approx. 4 EUR for the TDC chip, 5 passive components and some board space; I've actually reused everything from my principally similar frequency counter including the proto PCB made by JLC).
Practically eliminate means 100 picoseconds range that is so minuscule compared to the jitter from the GPS pulse output that one can entirely focus on that (getting rid of the added variance of the GPS pulse output).

Theboel:

--- Quote from: edigi on August 05, 2019, 10:57:12 am ---
--- Quote from: fourfathom on August 03, 2019, 08:09:51 pm ---What kind of specs are you looking for here?  I'm surprised that you can't get these deterministic delays with a CPLD, since 100MHz (and faster) internal clocking is pretty typical and with clocked outputs the delay variation will be within a couple of nanoseconds.

--- End quote ---

What I actually wrote that with CPLD you do get more deterministic delay than with FPGA (unless CPLD is internally uses an FPGA like architecture). No other clock is involved in my solution than the 10 MHz (the reference that is GPS disciplined) and the GPS pulse output.

Sure, that the biggest noise contributing factor is the jitter from the GPS pulse output (https://www.u-blox.com/sites/default/files/products/documents/Timing_AppNote_%28GPS.G6-X-11007%29.pdf), however it costs close to nothing to practically entirely eliminate the uncertainty of the GPS pulse period measurement in reference periods terms (approx. 4 EUR for the TDC chip, 5 passive components and some board space; I've actually reused everything from my principally similar frequency counter including the proto PCB made by JLC).
Practically eliminate means 100 picoseconds range that is so minuscule compared to the jitter from the GPS pulse output that one can entirely focus on that (getting rid of the added variance of the GPS pulse output).

--- End quote ---

Hi Edigi,
Some people think jitter from GPS module is not so important because when You averaging it to control let say OCXO with 100 second,  the jitter will attenuate so much especially when You use TIC but in my opinion there is nothing wrong with the best we could.
as far as I know TDC7200 can work up to 50MHz but I do not know how much trouble for You for multiply I assume 10MHz source to 50MHz even sampling 1PPS with 10Mhz will very good.

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