Low noise 0.01Hz-1+MHz amplifier project

[CurtisSeizert]

Interesting result and a nice transistor.

1/f corner is a decade lower than specified by Toshiba. 12pA/rtHz at 1Hz is only 10dB above OP37/LT1037, despite 50x higher collector current. It seems that good discretes can have a meaningful advantage over IC opamps in this area.


So it's still unclear where the unexpected noise comes from? I suppose you don't know what setup TI used to produce the datasheet figures?


edit
What software are you using to produce these plots? I'm trying to do some noise measurements and already wrote an Octave/Matlab script for it, but I'm not 100% confident in my DSP skills so it would help me to compare against known-good solutions.

I just use python - scipy for the FFT and matplotlib for the plots. Pandas for the csv stuff. Here is the code, but it is not pretty. I am ashamed to admit I usually just edit the display_spectrum function as needed. I have noticed that there is some dependence on how the lower end of the spectrum looks for different values of nperseg with the signal.welch function. It may be more accurate to make it correspond to more than two periods for the lowest frequency, but this is a good compromise between resolution at the low end and jaggedness at the top end. Also, the range of csv formats it accepts is pathetic. I don't know how to make that part better and I haven't really had the motivation to learn. Nonetheless, when I have checked this against datasheet plots or the implementation in Waveforms (for the ADP3450), it is reproduces them well. The Digilent spectrum analyzer seems to give a gain error of -12% very consistently, but when I export the time domain data from the scope and analyze it in python it gives accurate values of NSD, so it's not that the front end is out of calibration. I don't know why this is, so I only really use that FFT implementation if the absolute values don't matter.

Code: [Select]

import pandas as pd
from scipy import signal
import numpy as np
import matplotlib.pyplot as plt

class Wave:
    
    df = []
    timeseries = []
    gain = 1
    sfreq = 0
    timestep = 0
    vsd_smoothed = []
    freq_smoothed = []
    
    interval = 0
    
    vsd_check = []
    freq_check = []
    
    #voltnames and secnames are given as lists to enable matching with variously labeled
    #and formatted input data
    voltnames = ["v", "volt", "volts","voltage"]
    secnames = ["s", "sec", "seconds", "t", "time"]
    
    
    def __init__(self):
        self.fft = pd.DataFrame(columns = ("psd", "vsd", "freq", "dBc"), dtype = float)
        
    def readCSV(self, filename):
        self.df = pd.read_csv(filename, skipinitialspace = True, usecols = lambda x: x.lower() in self.voltnames) #Populate dataframe from csv
        self.df = self.df.assign(nV = self.df.mul(10**9)/self.gain) #convert volts to nV
        self.df = self.df.rename(columns={self.df.columns[0]: "V"}, errors="raise") #update column label
        
        self.timeseries = pd.read_csv(filename, skipinitialspace= True, usecols = lambda x: x.lower() in self.secnames, nrows=1000) #Get limited timeseries data
        if self.timeseries.size > 0:
            step = self.timeseries.diff()[self.timeseries.columns[0]].mean() #calculate the average difference between times
            self.set_timestep(step) #set timestep
    
    def save_trace_to_csv(self, filename):
        self.df.to_csv(path_or_buf = filename, columns = ["V"])
        
    def save_fft_to_csv(self, filename):
        self.df.to_csv(path_or_buf = filename, columns = ["vsd", "freq"])
    
    def set_timestep(self, timestep):
        self.timestep = timestep
        self.sfreq = 1/self.timestep
        
    def set_gain(self, gain):
        self.gain = gain
        
    def set_sfreq(self, sfreq):
        if sfreq <= 0:
            print("Error: Invalid Frequency")
            return 1
        else:
            self.sfreq = sfreq
            self.timestep = 1/self.sfreq
            return 0
    
    def calc_fft(self, f_low):
        if self.df.size == 0 or self.timestep == 0:
            return 1
        nperseg = 2*(1/(f_low*self.timestep))
        self.fft["freq"], self.fft["psd"] = signal.welch(self.df["nV"], fs=self.sfreq, nperseg = nperseg, window="hamming", average="median")
        self.fft["vsd"] = np.sqrt(self.fft["psd"])
        
    def calc_rms(self, f_low, f_high):
        i = int(0)
        rms = float(0)
        freq_step = self.fft["freq"][1] - self.fft["freq"][0]
        
        while self.fft["freq"][i] < f_low:
            i += 1
            
        while self.fft["freq"][i] <= f_high:
            i += 1
            rms += self.fft["psd"][i]*freq_step
        
        return np.sqrt(rms)
    
    def carrier_dens(self):
        return max(self.fft["vsd"])
            
        
        
    def display_spectrum(self, title=None):
        plt.figure(dpi=600)
        plt.plot(self.fft["freq"], self.fft["vsd"])
        plt.xscale("log")
        plt.yscale("log")
        #plt.ylim(top=10,bottom=0.1)
        plt.xlim(left=9,right=18)
        plt.xlabel('frequency [Hz]')
        plt.ylabel('Linear spectrum [nV/rt Hz]')
        plt.grid(visible=True, which="both", axis="both")
        plt.title(title)
        plt.show()
               
    def average_readings(self, numavg):
        self.timestep = self.timestep*numavg
        
        for i in range(0, int(len(self.df["nV"])/numavg-1)):
            avg = 0
            for j in range(0, numavg):
                avg += self.df["nV"][i*numavg + j]
            self.df["nV"][i] = avg/numavg
            avg = 0
        
    def plot_tdomain(self, time_start, time_stop, title):
        time = []
        nv = []
        lastpt = int(time_stop/self.timestep)
        firstpt = int(time_start/self.timestep)
        
        for i in range(firstpt, lastpt):
            time.append((i-firstpt)*self.timestep)
            nv.append(self.df["nV"][i])
            i += 1
        

        plt.figure(dpi=600)
        plt.plot(time, nv)
        plt.ylim(top=510,bottom=480)
        #plt.xlim(left=0,right=time)
        plt.xlabel('Time (s)')
        plt.ylabel('nV')
        plt.grid(visible=True, which="both", axis="both")
        plt.title(title)
        plt.show()
        ppnoise = max(nv) - min(nv)
        print("Peak to peak noise (nV): ", ppnoise)

      
w = Wave()
w.set_gain(10000)
w.readCSV("Experiments\HN4C51_6k745_Rs_50SPS_128kSa.csv")
w.set_sfreq(50)
w.calc_fft(0.01)

TI has a datasheet figure about how they measure the AC parameters, including NSD. I took a screenshot and attached it.

As for the noise sources, I have not checked the PNP duals (HN4A51). The current noise from that could be problematic. However, this is otherwise a very good transistor for current mirrors because it has as high an Early voltage as any small-signal PNP transistor I am aware of.

I took some more spectra for the HN4C51, and I was able to get a NF of about 2.5 dB with Rs = 1 (Ie had dropped to 5.68 mA at that point from battery discharge), so I played around with the model a little bit to get it to better reflect what I had seen. The one below reproduces the noise spectrum with Rs = 6k745 very well, but it is a bit too optimistic with the 1/f noise at Rs = 1R00. I added a value for KF and increased RB to 35. I added AF=1, which is the default value, though my calculation of the 1/f slope suggested 0.95. But the limited data I was working with, it seemed a bit shaky to reject the null hypothesis there. I wouldn't take this as gospel, but Toshiba hasn't gone to the trouble, so here we are. To be fair to Toshiba, the KF parameter is used in none of the BJT models included with LTSpice. The default value is zero, so none should show 1/f noise. I tested a few to check this, and all had flat NSD at low frequency.

Code: [Select]

.MODEL HN4C51 NPN(
+ LEVEL = 1
+ Kf = 0.0085f
+ Af = 1
+ IS = 1e-013
+ BF = 350
+ NF = 1
+ VAF = 276.3
+ IKF = 0.26
+ ISE = 1.37E-012
+ NE = 1.8
+ BR = 2.3
+ NR = 1
+ VAR = 100
+ IKR = 10
+ ISC = 2e-010
+ NC = 1.6
+ NK = 0.58
+ RE = 0.2
+ RB = 35
+ RC = 0.12
+ CJE = 1.435E-011
+ VJE = 0.75
+ MJE = 0.33
+ CJC = 5.714e-012
+ VJC = 0.74498
+ MJC = 0.22504
+ FC = 0.5
+ TF = 4.6e-010
+ XTF = 10
+ VTF = 5
+ ITF = 0.1
+ PTF = 0
+ TR = 10E-09
+ EG = 1.11
+ XTB = 1.4
+ XTI = 4
+ TRC1 = 0.01
+ TNOM = 25)

I think the major discrepancy between the simulation and reality is due to TI's model being too optimistic. With this bare-bones common source amplifier in LTSpice to check the noise (and compare with datasheet values), The 1/f corner is about 3 Hz, and the NSD at 100 mHz is only 6 nV/rtHz. Compare that to the datasheet noise spectral densities, where the 1/f corner is closer to 20 Hz. Simply editing the value of KF in their model from 0.2e-18 to 2e-18 actually gets you pretty close to the datasheet, but those spectra are too pessimistic. If you plug values into my LTSpice model, you can get an upper bound on KF of 0.5e-18 based on comparison to my data, and with two of these amplifiers built and tested (with indistinguishable 1/f noise), that is averaging 32 pairs of JFETs. That said, the noise figure of the JFETs in this topology is the matter at hand, so it is probably best to build something up to test it with less uncertainty. Perhaps rigging up one as a follower with a drain current of 400 uA would do the trick - the NF should be ~9 dB through the whole spectrum (a bit less because of Rg above the 1/f corner) and there's no issue of calibrating the gain.

Edit: Attached screencaps of the LTSpice simulation and the datasheet noise spectra.

[CurtisSeizert]

This is clearly not a "budget" project but good work overall! I did not fully yet check the (github) schematics but at least PSU section could need some attention from the protection point of view that you have nicely started. MBR0540 V_RRM(min) is rated 40V but the caps are 35V and at least LT30402 absolutely max is only 22V. MBR0520 - which could be safer call - has same footprint (if I remember correctly). Well, one could play certainly even safer with some other brand Schottky.

Much obliged for the review - I was hoping to get more criticism of elements outside the input stage. This is a hobby for me, so I don't really know all the industry best practices for power protection. The least safe part of the whole thing is definitely the battery. If the clips go on crooked, as they sometimes do, there is a possibility of shorting two cells together when you are popping one in or out. I have dealt with this on the current design with polyimide tape on the suspect ones, but this is not ideal. Keystone makes another variant for 21700 batteries that is plastic with leaf-spring type contacts, but they cost like $7 each in small quantities.

I don't know if a BQ77915 is appropriate as the only level of battery protection. Most of the decisions in that board were aimed at minimizing battery drain current while it is off. This necessitated a somewhat elaborate scheme for pulling the PRES pin high if the power switch is on or it is plugged in. I actually used a non-latching relay for the plugged in part because I had run out of patience for designing the nuts and bolts elements.

The charge cycle is actually terminated by OVP from the BQ77915, which was not my intention when I designed it. I need to investigate this because it is annoying, but it doesn't seem to be due to an overvoltage event on any of the cells or the pack as a whole.

This maybe wouldn't be obvious to someone who hasn't made one (and destroyed a battery board), but there should be a polyfuse or something on the GND connection to protect against accidentally shorting the shield frame to some other point on the battery board (BATT- was the culprit for me). In a future revision, the connection with the charger board (the rear panel) will be board-to-board so it doesn't rely on a wire harness to hold it in place. I will still use the Molex microfit connectors for that, so there is a positive lock.

I had not considered a lot of power rail protection to be necessary other than battery reverse polarity protection. The Schottky diodes are there in case one power rail fails or a regulator goes into OCP so the -4V3 rail does not pull the +5V4 rail far enough below GND to cause immediate trouble. I hadn't thought of them for possible overvoltage protection, but that may be worthwhile for instances like testing the board with a bench supply. I think I might need Zeners there though (in addition), because the LP2985 won't suffer more than 18V. The 35V Ta caps on the inputs are probably overkill. With 12V Zeners, I could just use more of the 47uF/16V molded Ta caps I use elsewhere.

[David Hess]

The Digilent spectrum analyzer seems to give a gain error of -12% very consistently, but when I export the time domain data from the scope and analyze it in python it gives accurate values of NSD, so it's not that the front end is out of calibration. I don't know why this is, so I only really use that FFT implementation if the absolute values don't matter.

The RBW (resolution bandwidth) of the measurement needs to be used to adjust the measurement to nV/SqrtHz.  This varies with FFT bin width and window function.

[Gerhard_dk4xp]

I always had these stability problems with the negative real part of the amplifier input impedance and tried to avoid feedback. Since gm goes with the square root of the drain current, I fed the source from a CCS with large electrolytics to force AC GND, much like the test circuit above. That was a complete disaster; on the output I could see nearly every electron that defected through the capacitor.

Oscons were worst; they created a noise corner in the 10s of KHz, and it was steeper than 1/f. I admit they were quite old. My FFT analyzer thanked with ADC overflows. Nippon Chemical high voltage ALU electrolytics were much better but still unusable. The only thing that kinda worked was a wet slug tantalum by AVX 4700u / 25V for ~ €100. At maybe half a volt of working voltage. Sprague ask for twice the price, btw. The corner was still at 30 Hz or so. These wet slug tantalums show a series resistance in strong contrast to the price.

cheers, Gerhard

[CurtisSeizert]

Preliminary data from the JFE2140 test shows I may have been wrong about the model. The 1/f corner of these things is insanely low, like a decade below what you would come up with from looking at the datasheet NSD curves. I am rerunning the calibration curves with more points to get decent looking curves down to 10 mHz, but I have attached the preliminary results, but approach these with some caution until I rerun the noise floor calibration and the 240R calibration. I have also attached the schematic of the test jig. Getting good LF spectra with this required me to put a towel and some foam insulation over the metal shielding box the whole setup was placed in. Within the shielding box, I put some lint-free wipes and a digikey bag over the JFET itself. The whole box had to be closed for about an hour before it would really settle. The Vgs tempco at this drain current is very significant compared to the noise of the JFET.

I think the degradation of the SNR of the LNA at low frequencies tells the story here - Magic and Kleinstein were right that the input stage is leaving a fair amount on the table below 1 Hz. This was an effect I saw in preliminary captures as well without targeting low frequencies, so this is not a fluke result. Also, I am confident in the accuracy of the data coming from this test setup, but I think that results like these warrant some additional checks, probably with n>1 for DUTs. This will take some time as each capture is 6 hours and settling is pretty significant on top of that. Also, it seems like TI is really burying the lede in the biggest way possible by reporting the NSDs they do in the datasheet and having their model give a truer representation of the exceptionally low 1/f corner of the JFET pair. Also, I don't have the spectrum saved, but the wideband noise is right where we would expect (with noise floor correction of the LNA) - 1.6 nV/rtHz.

Edit: Reattached the spectrum.

[Gerhard_dk4xp]

That's unfair. 33 People have seen the Noise Spectrum Density, and I get "404 - attachment not found" 

Edit: yes, it is re-attached, thanks!

[CurtisSeizert]

My results with better spectra for noise floor subtraction remained consistent with the ones I reported before. I attached the NSD down to 10 mHz. Recall, though, that the HP filter envelope gives somewhat greater than 3 dB attenuation at 10 mHz, hence the change in slope. As a verification of the technique for subtracting the noise floor of the instrument at relatively low SNR, I repeated the procedure with the internal 240R noise reference. It was 291 K during the capture, so the NSD should be flat at 1.97 nV/rtHz. For readability, I did some smoothing with splines (scipy.interpolate), but I kept this to a minimum and made sure that the result accurately captured the unsmoothed curves. There is an uptick in SNR for the JFE2140 at very low frequency, but I don't think that is increased noise of the JFE2140 near 10 mHz. It is probably an artifact of trying to measure single digit nVRMS noise for a Vgs with close to a 2 mV/K tempco. I may use a differential source follower measurement to cancel most of this temperature coefficient and give me 3 dB more SNR for future tests. By the way, the source resistor (12k) here is large enough to keep the follower close enough to unity gain for what we are doing - with gm of 4 mS, the voltage gain is 0.98.

As for design modifications of the amplifier that would not degrade the inherently low 1/f noise of the JFET pair, I am testing deletion of the current mirror right now. The current mirror actually gives very little increase in gain for the differential pair stage, and when you think about it, this makes a lot of sense. Any increase in the load impedance for the differential pair loads the emitters of the folded cascode, and when that load impedance is >>r_e, the effect approximately cancels. From simulations, the differential gain was 61.49 dB without the current mirror and 64.02 dB with them in. If you need that 2.5 dB back, which you don't, all you need to do is increase the load resistors for the folded cascode. This is doable because without the current mirror the phase margin is much better - about 90 degrees at a gain of 500 (it was about 65 degrees before, from memory). The point of this was to get rid of the current noise from the mirror, but even if that does not turn out to be the case the design is better without it.

[CurtisSeizert]

Deleting the current mirror did the trick. I appreciate the help on improving the design.

[David Hess]

Deleting the current mirror did the trick. I appreciate the help on improving the design.

Do you mean that you removed the current mirror at the output of the folded cascode?

This is doable because without the current mirror the phase margin is much better - about 90 degrees at a gain of 500 (it was about 65 degrees before, from memory).

Removing the current mirror halves the transconductance.  Does this alone explain the better phase margin?

For ICs removing the current mirror also removes its parasitic capacitances, however this does not apply in a discrete design.

The reduction in transconductance, removal of parasitic capacitances, and lower noise explain why high performance operational amplifiers typically do without a current mirror on the first stage.  I now wonder why a current mirror would be used at all; does it have any advantage?

[magic]

It is my recollection that there was no mirror under the folded cascode, only resistors. Current mirror was used to load the JFET pair.

It's curious that 3dB improvement near 0.1Hz is better than predictions based on measured HN4C51J base current noise. Maybe the complementary PNPs are noisier, or maybe the mirror had other problems too. One suspicious thing about it is the asymmetry of both base currents flowing into one drain; this not only causes offset but also makes the mirror sensitive to β drift (for any conceivable reason, perhaps temperature fluctuations, perhaps caused by LTP bias drift). OPA627 uses Darlington drivers (running on lean bias themselves) to merge individual mirror transistor base currents back into their corresponding collector currents.

Combination of current mirror and folded cascode can be redundant indeed - the FC already sets a constant voltage across drain resistors and hence constant current too. It only needs to be ensured that input resistance of FC emitters is order of magnitude lower than the value of drain resistors for more than 90% of drain AC current to enter the cascode. Since FC operating current can be set lower than the differential pair's, high load resistance and gain become practical.

From noise perspective, folded cascode looks like a differential pair - its base current noise flows (from emitters) into the drains, its differential voltage noise is impressed (by emitters) on drain resistors. Stability concerns aside, I would expect best results when folded cascode bias is adjusted for optimum noise figure with given drain resistors, particularly minding low frequencies. Possibly a well tuned implementation could outperform bipolar IC opamps, which was my own suggestion a few weeks ago. Not sure if a monolithic PNP pair would be advantageous, but there is a theoretical concern about asymmetric Vbe drift modulating drain resistor currents differentially.


Lastly, the folded cascode could replace the main cascode in its role of determining drain voltage and reducing drain voltage swings and Miller effect (the likely reason why adding the main cascode reportedly improved stability). However, it must be said that as long as the FC operates at lower current than the diff pair, its emitters will never have as low input resistance as a straight cascode and hence Miller elimination may be less effective. And I suspect some modifications could be necessary to the biasing and folded cascode servo circuitry.


edit
A random idea: use a current mirror, bias folded cascode bases to constant voltage, use the servo opamp to control current mirror bases instead.

Expected outcome:
1. Asymmetry of mirror base current is eliminated, it all flows into the opamp.
2. Base current noise remains a concern (appears at the drains by subtraction from collector currents).
3. Impedance seen by folded cascode emitters increases, decreasing any effect their Vbe drift or mismatch may have.

Depending on whether mirror current noise or other factors are dominant, this may be better or it may be worse

[Kleinstein]

The main point of the current mirror is to combine the differential signals to one current signal to use compensation with a mittler capacitor or similar. It is a nice way to get the sampe current on both sides.
With the OP-amp as a kind of differential integrator one does not really need the current mirror.
On the other side a well designed current mirror (low noise transistors and not too small emitter resistors - the larger the resistors the lower the noise, but also more voltage needed) the noise from the current mirror should be small compared to the JFET or other differential stage noise. Similar the kascode tansistors add a tiny bit of noise, but normally not significant. Usually it is not so much the transistors at the current mirror but the emitter resistors that add some noise, though still smaller than the main input transistor pair.  Alternative forms like folded kascode or 2nd differential stage would also need similar resistors - it is only for high frequencies that an inductor can be a real option.

In this case it looks like the HN4C51 transistors are not really low noise at the high current, at least not from the graph in the datasheet.

[magic]

The reduction in transconductance, removal of parasitic capacitances, and lower noise explain why high performance operational amplifiers typically do without a current mirror on the first stage.  I now wonder why a current mirror would be used at all; does it have any advantage?

Quite several modern TI opamps have active loading shown on simplified schematics: OPA827, OPA140, OPA209, OPA210, OPA211. These schematics certainly hide a lot (look at OPA627), but I doubt that they lie about active loading.

Possible benefits include:
- higher 1st stage output impedance and less sensitivity to 2nd stage voltage noise or nonlinearity
- increased overall open loop gain at low frequencies and DC
- lower voltage drop and wider common mode input range
- a transistor pair may take less area than long resistors

All except the last may be relevant to discrete amplifiers.

[David Hess]

The reduction in transconductance, removal of parasitic capacitances, and lower noise explain why high performance operational amplifiers typically do without a current mirror on the first stage.  I now wonder why a current mirror would be used at all; does it have any advantage?

Quite several modern TI opamps have active loading shown on simplified schematics: OPA827, OPA140, OPA209, OPA210, OPA211. These schematics certainly hide a lot (look at OPA627), but I doubt that they lie about active loading.

Possible benefits include:
- higher 1st stage output impedance and less sensitivity to 2nd stage voltage noise or nonlinearity
- increased overall open loop gain at low frequencies and DC
- lower voltage drop and wider common mode input range
- a transistor pair may take less area than long resistors

All except the last may be relevant to discrete amplifiers.

Since open loop gain at low frequencies is limited by thermal feedback, I wonder if active loads matter here anymore.  Once thermal feedback is accounted for, then it might matter.

The space saving would certainly matter for a gain cell type of application (324/358) where area (price) is everything.

Precision bipolar designs include input bias current cancellation which raises the input noise current anyway, so added noise from the current mirror would matter less.

[CurtisSeizert]

Deleting the current mirror did the trick. I appreciate the help on improving the design.

Do you mean that you removed the current mirror at the output of the folded cascode?

This is doable because without the current mirror the phase margin is much better - about 90 degrees at a gain of 500 (it was about 65 degrees before, from memory).

Removing the current mirror halves the transconductance.  Does this alone explain the better phase margin?

For ICs removing the current mirror also removes its parasitic capacitances, however this does not apply in a discrete design.

The reduction in transconductance, removal of parasitic capacitances, and lower noise explain why high performance operational amplifiers typically do without a current mirror on the first stage.  I now wonder why a current mirror would be used at all; does it have any advantage?

The current mirror I deleted was Q27 in the attached screenshot of the schematic. The current mirror was vestigial, like an appendix; it was necessary for high gain in the design iterations before inclusion of the folded cascode, and I kind of took its presence for granted after that. I don't think it has any advantages - the 3dB gain difference is recoverable by increasing the loads on the collectors of the folded cascode, and the gain is high enough as it is. I haven't really dug into why the phase margin is better yet because I have been busy taking captures and cleaning up the messes I have made setting up these experiments.

I think it is probably better to keep the current mirror out and keep the folded cascode if current noise is a concern, but I may be wrong about this. Any base current, as Kleinstein has reminded me, is emitter current that is not flowing through the collector, so if there's another pair of BJTs (other than the normal cascode) in the design, it would be best to have them running at a lower collector current, as the folded cascode does.

I have used the HN4C51 model I posted in simulations, both with and without a non-zero value of KF. With the value I had (0.0085f), the cascode pair contributes some amount to the noise of the input (at 10 mHz, it goes from about 6.6 to 7.2 nV/rtHz). With this new configuration, I can still use the SNR with noise of a JFE21140 (pair) measured with the LNA as an indication of how much it is feasible to improve the RTI noise, but with the mirror deletion, it seems we are pretty close to the point of diminishing returns at very low frequency. There is only so much capacitance that will fit on the board and only so large a value for the resistor used to GND the gate side of the AC coupling filter that is feasible to use without sacrificing settling time.

In this case it looks like the HN4C51 transistors are not really low noise at the high current, at least not from the graph in the datasheet.

In my hands, and in the configuration I tested, the part I looked at was very low noise at high current. With 1R00 base resistance (essentially diode connected at that point), the noise spectrum I took with the LNA (prior to deleting the current mirror) was about 3dB up from the noise floor all the way down to 100 mHz. I did not take a really long capture to get good data down to 10 mHz, but it seemed like that trend would continue. That is pretty quiet as long as you keep the source impedance low, but it is not as good as predicted from the model I posted. I would need to read more about the Gummel-Poon BJT noise model to get a better fit for both.

I don't know much about semiconductor design, but from what I do know, it seems that using active loads to keep on-die resistors small would matter a lot. The ADA4625 has a reasonably detailed circuit diagram (at least by comparison to what is usually disclosed in a datasheet), and they mention using passive loads for the first stage, but it is not clear how large they are. They aren't using a real cascode in this case, so there would be a limit as to how large the loads could be and still increase the gain, assuming that gos for their input pair is not remarkably high.