Distance between JTAG/SWD connector and MCU - what is too far?

[ninux]

Dear colleagues,

Recently, one of our embedded gurus told me that I have placed the JTAG connector too far from the MCU to enable decent speeds (approx 40 mm, see attachment). However, it worked just fine with the settings our customer is using.

When I designed the board, I checked all reference guides for the MCU (STM32F412), but there was no info about trace lengths for the JTAG.

I know that JTAG can go up to pretty high speeds but do you consider these speeds for all of your designs having JTAG? What is the rule of thumb here? Should the JTAG connector be right next to the MCU in every design? What would you consider too far away?

Thank you for your replies =)

[RoadRunner]

Dear colleagues,

Recently, one of our embedded gurus told me that I have placed the JTAG connector too far from the MCU to enable decent speeds (approx 40 mm, see attachment). However, it worked just fine with the settings our customer is using.

When I designed the board, I checked all reference guides for the MCU (STM32F412), but there was no info about trace lengths for the JTAG.

I know that JTAG can go up to pretty high speeds but do you consider these speeds for all of your designs having JTAG? What is the rule of thumb here? Should the JTAG connector be right next to the MCU in every design? What would you consider too far away?

Thank you for your replies =)

JTAG is not  that fast. 40 mm traces will not create issue for JTAG even in fastest mode. JTAG only goes few tens of Mhz.
It is common practice to put JTAG connector near to the target because of routing ease, definitely not because of speed.
If one put JTAG far away, Those JTAG traces need to routed on the board will criss cross with other traces, which only make layout a little bit hard.
Production programming/Test by a specific Tool/hardware/Test jig  is only reason i can think of to put JTAG connector away from Target on specific place.

Regards

[ataradov]

40 mm is nothing. The length does not matter that much. You want to be a bit more careful if you are using trace, but normal JTAG/SWD are quite tolerant to that stuff.

[Siwastaja]

Your "embedded guru" sounds like a con.

[ejeffrey]

The JTAG/swd cables I normally use are 15 cm.  An few cm on the board is no big deal.  I have run both significantly farther either to make the programming header more accessible or because I couldn't afford the board real estate closer to the target. 

[cmcraeslo]

I've designed around 30 different boards with stm32 SWD connection. Never really paid any attention to how the routing of the jtag/swd connector is. Never had a single problem with it (and i've been programming some of them live in a circuit in a running car).

[ninux]

40 mm is nothing. The length does not matter that much. You want to be a bit more careful if you are using trace, but normal JTAG/SWD are quite tolerant to that stuff.

Maybe he ment to say trace? But anyhow, the programmer cable is still several cm long. What would you change to have good performance for trace instead of just JTAG/SWD?

[ataradov]

For tracing you need to start thinking about making PCB traces equal in length. The exact length does not really matter. And you want them to be generally surrounded by a ground plane. Just general EMI considerations, nothing special.

Tracing debuggers still have 15-20 cm of ribbon cable, so additional few cm on the PCB won't change anything.

And even then, good tracing probes have delay compensation for all data lines, so it is even less critical. It is just annoying to do that.

[Vestom]

JTAG signals can be problematic. Especially if your probe has fast edges and your IC is a fast one (e.g. FPGA or fast CPU). The most typical problem is bad signal integrity resulting in runts or glitches on the TCK signal, which is an edge trigged clock signal.

However signal integrity is much more than just "distance to connector", and in principle there is no upper limit (within reason...) for the connector distance - as long as your signal integrity is OK. If you need to know more about "signal integrity", I can highly recommend this free book: http://thehighspeeddesignbook.com/.

(A little life-saver trick can be to add a series resistor (10-50 Ohms) close to the TCK pin, which can be tuned to form an RC low-pass filter with the input capacitance of the IC, if problems arises. )

But then again - with an STM32, I would not worry too much

[ninux]

JTAG signals can be problematic. Especially if your probe has fast edges and your IC is a fast one (e.g. FPGA or fast CPU). The most typical problem is bad signal integrity resulting in runts or glitches on the TCK signal, which is an edge trigged clock signal.

However signal integrity is much more than just "distance to connector", and in principle there is no upper limit (within reason...) for the connector distance - as long as your signal integrity is OK. If you need to know more about "signal integrity", I can highly recommend this free book: http://thehighspeeddesignbook.com/.

(A little life-saver trick can be to add a series resistor (10-50 Ohms) close to the TCK pin, which can be tuned to form an RC low-pass filter with the input capacitance of the IC, if problems arises. )

But then again - with an STM32, I would not worry too much

Thank you very much for your reply. Indeed, the signal integrity is key for any design and I try to avoid common issues by using a solid ground plane and a suitable PCB stack-up. Of course, there is always room for optimization =)

I just checked the schematic. Unfortunately, it seems that I only have pull-resistors and no resistors in series for any of the JTAG signals (see attachment). However, I will keep that in mind for the TCK pin in my next design!

[ataradov]

It is probably fine. This is 100 MHz device, so trace is probably works at max 50 MHz. It is not that fast.

And if you want to put series resistors, put them on all trace pins, not just clock. In reality it does not matter.

I would be more worried about those resistors to ground. I would remove those. They are not needed and have a chance to create issues.

[Vestom]

It is probably fine. This is 100 MHz device, so trace is probably works at max 50 MHz. It is not that fast.

When discussing signal integrity, it is not the frequency of the signal that matters, but the rise/fall-times of the edges. I have seen SI issues on 16 MHz clock signals with fast edges.

And if you want to put series resistors, put them on all trace pins, not just clock. In reality it does not matter.

TMS, TDO and TDI are level sensitive signals, so they are not as critical as TCK, which is edge sensitive. If board space is tight, a resistor on TCK should be prioritized.
[/quote]

I would be more worried about those resistors to ground. I would remove those. They are not needed and have a chance to create issues.

I do not agree. It is good practice to tie all inputs, unless the device is known to have reliable internal pull-up/down. What kind of issues do you foresee?

When giving advice, it is good practice not only to tell "what", but also "why", to make the receiver able to gain understanding and to evaluate the quality of the advice.

[ataradov]

Trace port uses DDR signaling, so both rising and falling edge of the clock matters. Introducing any asymmetry has potential to cause issues. From the MCU point  of view trace pins are always outputs, so pull-down resistors don't really do anything when trace is active. And if debugger creators feel like their debugger inputs need a stable level, they will include resistors on their end.

[ninux]

Trace port uses DDR signaling, so both rising and falling edge of the clock matters. Introducing any asymmetry has potential to cause issues. From the MCU point  of view trace pins are always outputs, so pull-down resistors don't really do anything when trace is active. And if debugger creators feel like their debugger inputs need a stable level, they will include resistors on their end.

To satisfy all possible opinions on this, one could prepare pull-down resistors as I did and the customer can decide if they want them populated or not I guess 

[Vestom]

Trace port uses DDR signaling, so both rising and falling edge of the clock matters. Introducing any asymmetry has potential to cause issues. From the MCU point  of view trace pins are always outputs, so pull-down resistors don't really do anything when trace is active. And if debugger creators feel like their debugger inputs need a stable level, they will include resistors on their end.

I agree, there is no need to put pull-down resistors on outputs (Though 10k is very unlikely to cause any asymmetry...)

Personally, I would rather have put series resistors on these signals to be able to trim impedance and provide a minimum of protection on a connector interface. But that was not the question