MC34063 gives me ADC noise on AVR! :(

[Alex]

Well, the MC34063 is not a PWM controller to be honest. It has a fixed duty cycle and applies that to the transistor if the output voltage is too low.

With reference to the datasheet, the issue is caused by the OSC block where the timing capacitor is connected. The OSC block charges and discharges the timing capacitor Ct with a constant current of 35 uA and 200 uA respectively. The voltage across the cap is an assymetric 'sawtooth' waveform (when the duty cycle is not 50%) like in figure 4 in the datasheet.
The ratio of currents is about 1/5.7, so with constant capacitance and voltage thresholds, the ratio of ramp up and down time is 1/5.7. The total maximum duty cycle is therefore 5.7/(1+5.7) = 5.7/6.7 = 0.851 or 85.1% !

You might be thinking that you can reduce the off time (ramp down) by selecting a smaller capacitor, but will also reduce the on time (ramp up). The app note AN920/D gives a way to increase the duty cycle but it uses germanium parts which, to be fair, eliminates the purpose of using an MC34063.

[scrat]

I see, the upper limit is because the reset control dominates and is generated once a period at a given instant. I didn't look so good at the functional schematic. At this point, I wonder why they decided to do so, but this is another story.

However, the 34063 is a -strange- PWM controller, since it modulates the duty-cycle depending on how much the output is lower than the reference. The strange thing (IMHO) is that they used a kind of negative logic: instead of turning on the switch synchronously and switching off when the output is high, it behaves viceversa.

[Alex]

You got it, the timing capacitor cannot instantly discharge forcing D<100%.

Have a better look at the diagram below again, it is the MC34063 connected as a buck converter. Same principles appy.



You will notice that what appears to be an op-amp that generates an error signal by comparing a reference and a fraction of the output, is in fact a comparator driving a logic gate.

In other words theMC34063 does not generate an error signal proportional to the output. It's a simple Yes/No signal. I think this topology is called 'simple switching' or 'switching' regulator but dont quote me on this. Maybe someone can confirm.

The signal can become Yes asyncronously. Say it becomes Yes at the end of the timing capacitor voltage ramp down. During the next cycle it will initiate an On cycle. In the case of a boost converter the output voltage continues to drop when the inductor charges, therefore the comparator still outputs a Yes. As the output transistor can only be switched off during the ramp down, there is a scenario where much more energy is stored in the inductor than needed leading to overshoot at the output voltage if it wasnt for the current sense resistor. If excessive current is sensed, the charging current for the capacitor is increased shortening the remaining ramp up time.

If there is any modulation on the pulse width, it is purely due to syncronisation of the output voltage drop with the sawtooth waveform. That, combined with the low switching frequency of 100kHz max, makes me think this regulator will give poor performance in pulsed applications if a monster output cap is not used.

Now compare with proportional control from an LM2588:

[scrat]

It behaves somewhat like a sampled-time linear controller, with duty-cycle limited to 85% very high gain (which depends on the output capacitance and output current).
Imagine that it samples the error value at the rising edge of the oscillator (the length of the off period at the start is proportional to how much the output is over the reference, since the output capacitance discharges when the switch is off).

Now I see why the duty-cycle limit is there: into a boost converter, if there was not a limit, it would have been highly unstable (as you described above) maintaining the switch on for all the time, when the output was low. Thanks to the duty limit, this doesn't happen, even without the current sensing (which is not needed, in fact, as I experimented).

[jahonen]

Can't it be described shortly without philosophizing by just saying that internal oscillator runs with 85% duty cycle if sensed voltage is below the reference and oscillator is completely off when sensed voltage is above the reference? I think it can be seen from the attached scope screenshot (measured from the switch node).

It also explains why the ripple is so peculiar, there are times where switching frequency drops very low (long time between bursts).

Regards,
Janne

[scrat]

Can't it be described shortly without philosophizing by just saying that internal oscillator runs with 85% duty cycle if sensed voltage is below the reference and oscillator is completely off when sensed voltage is above the reference? I think it can be seen from the attached scope screenshot (measured from the switch node).

It also explains why the ripple is so peculiar, there are times where switching frequency drops very low (long time between bursts).

Regards,
Janne

Well, it can have duty-cycle between zero and the maximum, since it can switch on AFTER the sync from the oscillator.
That was just my view of the thing, a model that (for me) gives best insight into the behaviour. I think that a lower cap value (and an additional filter, as in one example in the app note) could avoid that oscillation, at least for a range of load values.

[Alex]

Great info guys, thanks for your help exhausting this issue. I would have not brought this up if I had not seen a working (!) published design in a popular electronics mag. Hopefully this will help eliminate such designs.

Alex