| Electronics > Projects, Designs, and Technical Stuff |
| Hardware Frequency detector (for audio) |
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| RJSV:
An experimental circuit module uses synchronous detection, on a discrete set of samples. For a basic lowest rate of 220 hz, a buffer of 20 samples provides a delay line having exactly one half cycle time (about 2.2 msec). Each detector channel takes a discrete sample, delayed by the one half cycle time, subtracting it from the current analog sample. Circuitry has a rich mix, of analog and digital, using the CD4017 decimal counter, for example. That is a synchronous action , working to both favor one frequency (220 hz, at 4.5 msec. cycle period), and also working to reject, on average, other frequencies presented to the module input. A higher level circuit controls the process, checking each of 20 phases, during the 1/2 cycle time 'Contest' period. Contest 'winner' is expressed by sending RESET to the modulo-20 counter; Thus counter zero represents plus 90 degrees of phase, the maximum of a hoped-for detection. Now looking at another detection channel, using the delay line tap 'T19', that shorter half-cycle is approx. 12 cycles per second higher, the formula is to use the 8800 hz discrete interval clock, divided by number of samples back the delay is. The highest detection uses 10 intervals back, thus also having 10 possible phase choices (to try). The resulting range, of the full 10 channel detection module, is from 220 hz up to approaching 440 hz (actually less) for an approximate range of one octive (baritone). MORE TO FOLLW< Thanks |
| RJSV:
The Frequency detector has a very 'wide' output format: One option keeps each detection channel separate. In the 3 lines for each channel there is a pulsed line, signifying a 2X clock for a sine wave (generator). A second analog line signifies the amplitude info, while a third line conveys 'Signal Present'. Note the convienience , that clock divider(s) can be used, to bring an ultimate pitch down an octave, or two octaves. Thoughts of mixing all ten channel pulse trains don't pen out: likely producing copious spurious output frequencies (but perhaps interesting). A (good) recreational designer benefits from lessons learned from mistakes, sometimes; always keen to learn! A key aspect here, is the lack of some explicit encoded phase output, leaving each channel as-is. The justification is the so-called 'Trombonist' theory; if the musician skoots his chair back, the phase (of his sound) is different. But no one cares, or notices. Early design had (only) 6 output channels (for musical notes), where a complex competition / ranking scheme (hopelessly) burdened the works. Sorry to present this in sections, but cheerfully answer any ques, thanks |
| mark03:
This would be much easier to follow, if you could post the schematic. I take it this is implemented with discrete logic and some kind of switched-capacitor circuit, since you are talking about samples and delay lines. Wouldn't it be easier to perform this work in software instead? |
| boB:
Detecting a single fundamental frequency, right ? |
| RJSV:
boB and mark, I have some answers, following. Unfortunately, had laptop meltdown yesterday, on LIBRARY computer now, ah shucks... The frequency detector project has a 'front end' section, designed for a whole set of separate frequencies, not just the single, base (chosen to be 220 hz, that is the A note right below middle C). Current choice has 10 separate channels, each with a modulo counter (exclusively using CD4017 counters). That brings some efficiency, as every detection channel is served by the 'Ring Buffer'. A simple pulse, 'READ NEXT VALUE' serves to enable a switched capacitor. It involves a complicated / bulky digital 'Barrel Shifter' method. The actual frequencies where detection is attempted are as follows: Discrete clock rate divided by number of delay samples back the channel is using, and divided by 2. Each delay line tap is labled T20, T19, T18, T17, T16, T15, T14, T13, T12, and lastly T11. So lets pick T15, for example. The T15 delay line tap is for detecting 293 hz, meaning that a new analog front-end system input is being saved, to a capacitor (sample and hold) every (approx.) 114 micro-seconds, and that tap T15 produces a delay equal to 15 of those discrete action times. That's a mouthful. Readers may be starting to suspect: This thing is gonna need a PC board the size of a small pizza! Perhaps a good candidate for a FPGA project (that's a user programmed gate array). Also, obviously revealing just how valuable a 'one dollar cost' PIC chip setup can be, doing all this with ease !! So a main motivation (for this design project) turns out to be a curiousity question: Just HOW does a Fast Fourier Transform (or FFT) do its magic ? I'd like to post, first, a schematic of the analog front-end, where each output of a CD4017 digitally enables a particular capacitor. Not real strong on FET use, the system brings one capacitor leg to 3.5 volts. Each of the 20 capacitors is bussed together, with one leg attatched to the 'enable' logic, allowing for both current directions charge or discharge. Not sure how to import some hand drawn stuff, VIA my flip-phone camera. Readers can visualize the system as resembling FFT structure, or actually; 'half' of an FFT buffer, where real-time operation is providing or filling in the second half, of the sample stream. In other words, instead of all the samples provided off-line to a software routine, this (hardware) method will store a string of samples, during the 'NEGATIVE' half-cycle, and proceed to process each available pair (current sample minus delayed sample), as time goes thru the 'POSITIVE' half-cycle. Now for a crucial bit of 'learning': The realization that there usually is going to be NO clue where or what phase any content has, often regardless of visable waveform(s). The hardware system simply guesses and checks, trying each (phase of synchronous detection), and keeping track of 'best detection, so far'. A simple RESET is issued in that case, to the particular Modulo counter for the channel (the T15 tap example sends RESET to the modulo-15 channel counter.) Thanks for your time. This is a big project, and I could use some training on FET's and on sample-hold circuits. - - Rick-Jack |
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